[PATCH] D66822: Hardware cache line size builtins

[Zoe Carver via Phabricator via cfe-commits]

zoecarver created this revision.
Herald added a reviewer: jfb.
Herald added subscribers: cfe-commits, kbarton, aheejin, javed.absar, nemanjai.
Herald added a project: clang.

Creates the `__builtin_hardware_destructive_interference_size` and `__builtin_hardware_constructive_interference_size` builtins proposed by @jfb [[ here | http://lists.llvm.org/pipermail/cfe-dev/2018-May/058073.html ]]. These builtins can be used to implement [[ P0154 | http://wg21.link/P0154 ]] in libc++ and other standard libraries. My implementation switches on the target triple to get the max cache line size for that target. I am not sure if this is the best way to implement these builtins, but it will ensure that there is not an ABI break.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D66822

Files:
  clang/include/clang/Basic/Builtins.def
  clang/lib/AST/ExprConstant.cpp
  clang/test/Sema/builtins.c
  clang/test/SemaCXX/builtin-hardware-interference-size-aarch.cpp
  clang/test/SemaCXX/builtin-hardware-interference-size-amd.cpp
  clang/test/SemaCXX/builtin-hardware-interference-size-arm.cpp
  clang/test/SemaCXX/builtin-hardware-interference-size-nvptx.cpp
  clang/test/SemaCXX/builtin-hardware-interference-size-ppc.cpp
  clang/test/SemaCXX/builtin-hardware-interference-size-unknown.cpp
  clang/test/SemaCXX/builtin-hardware-interference-size-x86.cpp

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