[PATCH] D64739: [SVE][Inline-Asm] Add support to specify SVE registers in the clobber list

[Kerry McLaughlin via Phabricator via cfe-commits]

kmclaughlin updated this revision to Diff 210821.
kmclaughlin retitled this revision from "[SVE][Inline-Asm] Add support to clang for SVE inline assembly" to "[SVE][Inline-Asm] Add support to specify SVE registers in the clobber list".
kmclaughlin added a comment.

- Removed typo fixes from this patch
- Consolidated the tests in aarch64-sve-inline-asm.c into one test & fixed formatting
- Added a test without +sve to ensure we get the correct diagnostic


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64739/new/

https://reviews.llvm.org/D64739

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/test/CodeGen/aarch64-sve-inline-asm.c


Index: clang/test/CodeGen/aarch64-sve-inline-asm.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-inline-asm.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -target-feature +sve -o - %s | FileCheck %s -check-prefix=CHECK-SVE
+// RUN: not %clang_cc1 -triple aarch64-none-linux-gnu -S %s -o - 2>&1 | FileCheck %s -check-prefix=CHECK-ERROR
+
+long test_sve_asm() {
+  long t;
+
+  asm volatile(
+      "ptrue p0.d\n"
+      "ptrue p15.d\n"
+      "add z0.d, p0/m, z0.d, z0.d\n"
+      "add z31.d, p0/m, z31.d, z31.d\n"
+      : "=w"(t)
+      :
+      : "z0", "z31", "p0", "p15");
+  // CHECK-SVE: "=w,~{z0},~{z31},~{p0},~{p15}"
+  // CHECK-ERROR: error: instruction requires: sve
+
+  return t;
+}
Index: clang/lib/Basic/Targets/AArch64.cpp
===================================================================
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -351,10 +351,19 @@
     "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
     "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
 
-    // Vector registers
+    // Neon vector registers
     "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
     "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
-    "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
+    "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
+
+    // SVE vector registers
+    "z0",  "z1",  "z2",  "z3",  "z4",  "z5",  "z6",  "z7",  "z8",  "z9",  "z10",
+    "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
+    "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
+
+    // SVE predicate registers
+    "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",  "p8",  "p9",  "p10",
+    "p11", "p12", "p13", "p14", "p15"
 };
 
 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {


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