[PATCH] D63437: [CodeGen][ARM] Fix FP16 vector coercion

[Mikhail Maltsev via Phabricator via cfe-commits]

miyuki added a comment.

In D63437#1546312 <https://reviews.llvm.org/D63437#1546312>, @ostannard wrote:

> This doesn't look like the right pace to fix this - the backend can handle vectors of i8 and i16, which are also not legal types, so why can't it correctly handle vectors of f16?


IIRC, we decided to handle this in the frontend for consistency with scalar fp16 handling: https://reviews.llvm.org/D49987


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D63437/new/

https://reviews.llvm.org/D63437