[PATCH] D63437: [CodeGen][ARM] Fix FP16 vector coercion

[Oliver Stannard (Linaro) via Phabricator via cfe-commits]

ostannard added a comment.

This doesn't look like the right pace to fix this - the backend can handle vectors of i8 and i16, which are also not legal types, so why can't it correctly handle vectors of f16?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63437/new/

https://reviews.llvm.org/D63437