[all-commits] [llvm/llvm-project] c78147: AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Wed Jul 15 07:43:03 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c78147a9198c45ac1020dfc1d5524d158470309e
      https://github.com/llvm/llvm-project/commit/c78147a9198c45ac1020dfc1d5524d158470309e
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-merge.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/select-merge-values-build-vector-s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shader-epilogs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-divergent-addr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-uniform-addr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll

  Log Message:
  -----------
  AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (48) (#209756)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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