[all-commits] [llvm/llvm-project] f1cb3d: AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Wed Jul 15 07:40:28 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f1cb3d330c03827247468b4c0437e86ad0b286ad
      https://github.com/llvm/llvm-project/commit/f1cb3d330c03827247468b4c0437e86ad0b286ad
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir

  Log Message:
  -----------
  AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (47) (#209755)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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