[all-commits] [llvm/llvm-project] 567c6a: AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Wed Jul 15 05:47:27 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 567c6a7589fe9f29882d60ac2ddedc2f33bd80c1
      https://github.com/llvm/llvm-project/commit/567c6a7589fe9f29882d60ac2ddedc2f33bd80c1
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-returnaddress.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sbfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sopc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-packed.xfail.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sextload-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.invalid.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zextload-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/known-bits-sbfe.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/known-fpclass-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir

  Log Message:
  -----------
  AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (42) (#209732)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications

More information about the All-commits mailing list