[all-commits] [llvm/llvm-project] 9744b4: [CIR][AMDGPU] Add support for AMDGCN rsq and rsq_c...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Thu Jul 16 07:53:53 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpadd-umaxuminsmaxsmin-as-main-opcodes-for-copyables
Home: https://github.com/llvm/llvm-project
Commit: 9744b475e28e180599fd1a42d956f74b0a1aaed8
https://github.com/llvm/llvm-project/commit/9744b475e28e180599fd1a42d956f74b0a1aaed8
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN rsq and rsq_clamp builtins (#197349)
Adds codegen for the following AMDGCN reciprocal square root builtins:
- __builtin_amdgcn_rsq (double)
- __builtin_amdgcn_rsqf (float)
- __builtin_amdgcn_rsqh (half)
- __builtin_amdgcn_rsq_bf16 (bfloat16)
- __builtin_amdgcn_rsq_clamp (double)
- __builtin_amdgcn_rsq_clampf (float)
These are lowered to the corresponding `llvm.amdgcn.rsq` and
`llvm.amdgcn.rsq.clamp` intrinsic calls.
Commit: 567c6a7589fe9f29882d60ac2ddedc2f33bd80c1
https://github.com/llvm/llvm-project/commit/567c6a7589fe9f29882d60ac2ddedc2f33bd80c1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-returnaddress.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sopc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-packed.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/known-bits-sbfe.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/known-fpclass-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (42) (#209732)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 2746fc6981516c9e26dbdaa7ba254279d391b534
https://github.com/llvm/llvm-project/commit/2746fc6981516c9e26dbdaa7ba254279d391b534
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-splat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctls.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp-s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (43) (#209733)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 42605e7b341ccbc6b2486e2ced82386f099c476a
https://github.com/llvm/llvm-project/commit/42605e7b341ccbc6b2486e2ced82386f099c476a
Author: ioana ghiban <ioana.ghiban at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
M mlir/test/Dialect/MemRef/elide-reinterpret-cast.mlir
Log Message:
-----------
[mlir][memref] Support truncating copied dims to non-unit in reinterpret_cast elision (#209536)
Relax the `memref.copy`through `memref.reinterpret_cast` rewrite to
support same-dimension slices where strictly one non-unit source
dimension size is truncated to a smaller non-unit result dimension.
Previously, the rewrite only supported truncating to unit size:
```mlir
memref<1xMxNxf32>
to memref<1xMx1xf32, strided<[M*N, N, 1], offset: OFF>>
```
This change relaxes constraints to also support:
```mlir
memref<1xMxNxf32>
to memref<1xMxKxf32, strided<[M*N, N, 1], offset: OFF>>
```
where `K < N`.
The rewrite remains conservative:
* source must have identity layout,
* result strides must match the source identity strides,
* offset must be static for non-scalar results, and
* copied slice must be in bounds.
Assisted-by: Codex (refine PR description).
Commit: 0350a23a8bbc091e646406a2aaeafa35dc0216d3
https://github.com/llvm/llvm-project/commit/0350a23a8bbc091e646406a2aaeafa35dc0216d3
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/WrapperFunction.h
M orc-rt/test/unit/WrapperFunctionBufferTest.cpp
Log Message:
-----------
[orc-rt] Fix WrapperFunctionBuffer empty range construction (#209751)
orc_rt_CreateWrapperFunctionBufferFromRange(const char *, size_t) left
the constructed buffer's data member uninitialized when the size
argument was zero. This could result in the returned buffer having a
non-null data field and a zero size field, which is a (malformed)
out-of-band error value, not an empty buffer.
Update orc_rt_CreateWrapperFunctionBufferFromRange to zero-initialize
the data field so that the size == 0 case yields a correctly formed
empty buffer.
Commit: 653c1dab3774d0cf02bb9fc8c469bbd356aff885
https://github.com/llvm/llvm-project/commit/653c1dab3774d0cf02bb9fc8c469bbd356aff885
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
Log Message:
-----------
[X86] combineINSERT_SUBVECTOR - enable shuffle combining of insertsub(extractsub(shuffle),extractsub(shuffle)) patterns (#209735)
Allows combineX86ShuffleChainWithExtract to more consistently fold
patterns from wider sources
Commit: 4b66bacd1fdf02803509b744034f3ab09945157c
https://github.com/llvm/llvm-project/commit/4b66bacd1fdf02803509b744034f3ab09945157c
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/PropertiesBase.td
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Record.cpp
M clang/lib/AST/ByteCode/Record.h
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaType.cpp
A clang/test/AST/ByteCode/virtual-bases-codegen.cpp
A clang/test/AST/ByteCode/virtual-bases.cpp
M clang/test/CXX/drs/cwg16xx.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg6xx.cpp
M clang/www/cxx_status.html
Log Message:
-----------
[clang][ExprConst] Support virtual bases in C++26 (#204289)
Add support for virtual bases in constant expressions (P3533R2) to both the current constant interpreter as well as the bytecode interpreter.
Commit: 706db1e0959f45d6392edd2ad196a4ea38bb99d3
https://github.com/llvm/llvm-project/commit/706db1e0959f45d6392edd2ad196a4ea38bb99d3
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
Log Message:
-----------
[mlir][tosa] Add support for MXFP row_gather (#207933)
Adds profile compliance support for MXFP row_gather.
Commit: 4584a6489341b4fe7762991e65f98467ffe4c699
https://github.com/llvm/llvm-project/commit/4584a6489341b4fe7762991e65f98467ffe4c699
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.cpp
Log Message:
-----------
[lldb][AArch64][NFC] Make watchpoint adjustment more clear (#209483)
NativeRegisterContextDBReg_arm64::AdjustWatchpoint has a way of
adjusting the range of a watchpoint but it took me a while to figure out
how it worked. I've rewritten it in a way I think is easier to follow,
with more explanatory comments.
It turns out that this adjustment results in us only using a subset of
what the hardware allows.
* You don't have to select a continuous range of bytes (1, 2, 3). You
can select (1, 4) for example.
* The address can be 4 byte aligned, in which case only 4 bits of the
byte select apply (though you can set up an equivalent watch with 8 byte
alignment and a different 8 bit BAS value).
Commit: 2c978fa06d19095c0003508b8dac084689b12e78
https://github.com/llvm/llvm-project/commit/2c978fa06d19095c0003508b8dac084689b12e78
Author: Caroline Newcombe <caroline.newcombe at hpe.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Lower/Support/Utils.cpp
M flang/test/Integration/OpenMP/copyprivate.f90
M flang/test/Integration/OpenMP/private-global.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-teams-distribute-private-adjustable-array.f90
M flang/test/Lower/OpenMP/copyprivate.f90
M flang/test/Lower/OpenMP/delayed-privatization-array.f90
M flang/test/Lower/OpenMP/lastprivate-equivalence.f90
M flang/test/Lower/OpenMP/loop-directive.f90
M flang/test/Lower/OpenMP/parallel-private-clause.f90
A flang/test/Lower/OpenMP/private-array-boxing.f90
M flang/test/Lower/OpenMP/private-commonblock.f90
M flang/test/Lower/do_concurrent_local_assoc_entity.f90
Log Message:
-----------
[flang][OpenMP] Avoid boxing constant-size trivial private arrays (#208315)
Part of #208086. `privatizeSymbol` (used for both OpenMP privatization
and `do concurrent` locals) currently boxes every array as a workaround
for `fir.array` not being directly `alloca`-able in the OpenMP→LLVMIR
translation. This PR carves out the common case: a constant-shape array
of trivial intrinsic elements (e.g. `real(8) :: xx(3)`) is now
privatized unboxed, as a plain `fir.array`.
Commit: 2975dac23e684748ae1051e6c1112aa53d7aea2c
https://github.com/llvm/llvm-project/commit/2975dac23e684748ae1051e6c1112aa53d7aea2c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/test/Shell/helper/toolchain.py
M lldb/test/Shell/lit.cfg.py
Log Message:
-----------
[lldb] Drop support for using the external shell
The lit external shell is going to be removed soon, so drop support for
using it to run the LLDB tests.
Reviewers: DavidSpickett, JDevlieghere, petrhosek, ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/209627
Commit: a4d12bf0c2ab2acfd772a8fd6ad216e3a17e5c49
https://github.com/llvm/llvm-project/commit/a4d12bf0c2ab2acfd772a8fd6ad216e3a17e5c49
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/cmake/modules/FindPythonAndSwig.cmake
Log Message:
-----------
[lldb][Windows] Enforce Python 3.11 (#209759)
https://github.com/llvm/llvm-project/pull/191159 recommended Python 3.11
or later. Now that llvm 23 has branched, we can enforce Python 3.11 as
the minimum requirement.
Commit: 25682c3470410534c59708d7d3e2c9248802485f
https://github.com/llvm/llvm-project/commit/25682c3470410534c59708d7d3e2c9248802485f
Author: Access <ShootingStarDragons at protonmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/unittests/PrerequisiteModulesTest.cpp
Log Message:
-----------
[clangd] highlight import and export keywords for C++20 modules (#204511)
Add syntax highlighting for C++20 module `import` and `export` keywords.
Note: Highlighting of the `export` keyword in a module export statement is not possible, because such statements don't appear in the AST
Commit: 9a4deccf90ae914aa6d99acfff44b24bc5dfcb5c
https://github.com/llvm/llvm-project/commit/9a4deccf90ae914aa6d99acfff44b24bc5dfcb5c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/CMakeLists.txt
A llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
A llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
Log Message:
-----------
[WebAssembly] Introduce CodeGenPassBuilder
This is the equivalent of TargetPassConfig for the NewPM. This currently
mirrors the existing TargetPassConfig as close as possible, but with
TODOs for passes that have not been ported to the NewPM.
Reviewers: aheejin, sbc100, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/208983
Commit: f4452848f0a5e827f5732ab390099d7d90084ca0
https://github.com/llvm/llvm-project/commit/f4452848f0a5e827f5732ab390099d7d90084ca0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyAddMissingPrototypes.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/test/CodeGen/WebAssembly/add-prototypes.ll
Log Message:
-----------
[WebAssembly] Port WebAssemblyAddMissingPrototypesPass to NewPM
Standard pass porting.
Reviewers: dschuff, aheejin, sbc100
Pull Request: https://github.com/llvm/llvm-project/pull/208985
Commit: f69748cd80db74bcd81834b4bba8749fc508f99f
https://github.com/llvm/llvm-project/commit/f69748cd80db74bcd81834b4bba8749fc508f99f
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyFixFunctionBitcastsPass to NewPM
Standard pass porting.
Reviewers: aheejin, dschuff, sbc100
Pull Request: https://github.com/llvm/llvm-project/pull/208986
Commit: 80314ec06f15e7a0bb4b55380e50b2e529c5b0f7
https://github.com/llvm/llvm-project/commit/80314ec06f15e7a0bb4b55380e50b2e529c5b0f7
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/mman/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 36c6568 (#209689)
This fixes 36c6568b04aff4e1cf00a60570ab4a4344692920.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=36c6568b04aff4e1cf00a60570ab4a4344692920
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 491539a8b801aad5706cc32fc54a319791d57a91
https://github.com/llvm/llvm-project/commit/491539a8b801aad5706cc32fc54a319791d57a91
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyOptimizeReturned.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyOptimizeReturnedPass
Standard pass porting for the NewPM.
Reviewers: sbc100, dschuff, aheejin
Pull Request: https://github.com/llvm/llvm-project/pull/209036
Commit: 0d93f2aec0b4847761bd8458b7847ce37b85cf03
https://github.com/llvm/llvm-project/commit/0d93f2aec0b4847761bd8458b7847ce37b85cf03
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/SemaCXX/enable_if.cpp
Log Message:
-----------
Fix references to complete types in attribute references (#209537)
This is a regression from #197215.
Attributes are not REALLY in the body of a function (though the name of
said function is... awkwardly inaccurate at best), but still need to pay
attention to the completeness of their references. As a result, we
weren't marking the expression as invalid, but were also trying to
evaluate it.
This patch fixes this in 2 ways. First, we re-add the
CXXThisTypeOverride check, but except constant substitution, since that
has some additional 'this' behavior from #197215. x
Secondly, we also make the constant evaluator give up on incomplete
types when handling an L value member. This stops us from trying to
evaluate the value if it is incomplete during template instantiation,
when the type is incomplete. We don't diagnose, since it is still
potentially a constant expression, but isn't currently one.
Fixes: #199527
Commit: 5fcfb4d168eae3e78da8d0f7649bf08a338eff42
https://github.com/llvm/llvm-project/commit/5fcfb4d168eae3e78da8d0f7649bf08a338eff42
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/test/CodeGen/WebAssembly/lower-em-exceptions-allowed.ll
Log Message:
-----------
[WebAssembly] Port WebAssemblyLowerEmscriptenEHSjLjImpl
Standard NewPM pass porting.
Reviewers: dschuff, sbc100, aheejin
Pull Request: https://github.com/llvm/llvm-project/pull/209040
Commit: c2da010159cc318b5fdba4a1fc7deef9438e749d
https://github.com/llvm/llvm-project/commit/c2da010159cc318b5fdba4a1fc7deef9438e749d
Author: David Young <davidayoung at meta.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/src/string/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/mman/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/resource/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/unistd/BUILD.bazel
Log Message:
-----------
[libc][bazel] Add missing hdr/*_macros deps to test targets (#209761)
Commit b790c5cd2679 (#209449) switched several libc tests to include the
hdr/*_macros.h proxy headers and updated the CMake build accordingly,
but did not update the Bazel overlay. As a result, the Bazel libc test
targets include hdr/*_macros.h (and, via shared headers,
hdr/sys_mman_macros.h) without declaring the corresponding
//libc:hdr_*_macros dependencies, breaking the Bazel build with 'file
not found' / module layering errors.
Mirror the CMake dependency additions into the Bazel overlay so each
test target that includes an hdr macro header depends on the matching
//libc:hdr_*_macros (and //libc:types_struct_rlimit) target.
First found trying to land (#209747).
bazel changes assisted with: claude
cannot build with bazel locally so relying on CI to confirm green
Commit: 044f8a1f151f935d2e718faa5b1d7cb8e8f52bec
https://github.com/llvm/llvm-project/commit/044f8a1f151f935d2e718faa5b1d7cb8e8f52bec
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyReduceToAnyAllTrue.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyReduceToAnyAllTruePass
Standard NewPM pass porting. Made a little bit annoying by the module
caching that I'm not sure helps much, but I've left it in.
Reviewers: aheejin, dschuff, sbc100
Pull Request: https://github.com/llvm/llvm-project/pull/209043
Commit: 868e3b898dcf243f97885ce0d857a2827f4d1fa3
https://github.com/llvm/llvm-project/commit/868e3b898dcf243f97885ce0d857a2827f4d1fa3
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
Log Message:
-----------
[AMDGPU] Fix set_inactive known bits to intersect both operands (#201817)
SimplifyDemandedBitsForTargetNode grouped amdgcn_set_inactive with the
single-source readfirstlane/readlane/wwm, taking known bits from operand
1 only
Handle the data from the operand 2 inactive lanes as well
Commit: 8396c758875a11a57a4b6a2b6b06b719c1b2ab1b
https://github.com/llvm/llvm-project/commit/8396c758875a11a57a4b6a2b6b06b719c1b2ab1b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyRefTypeMem2Local.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyRefTypeMem2LocalPass
Standard NewPM pass porting.
Reviewers: sbc100, aheejin, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/209044
Commit: 7e80bca9c9130a49ded8ac500d19942928c3564b
https://github.com/llvm/llvm-project/commit/7e80bca9c9130a49ded8ac500d19942928c3564b
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libsycl/test/basic/parallel_for_indexers.cpp
Log Message:
-----------
[libsycl] Add missing include to test (#209722)
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 8a41c1f77732d18eae12409b572fc926df29062b
https://github.com/llvm/llvm-project/commit/8a41c1f77732d18eae12409b572fc926df29062b
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
Log Message:
-----------
[mlir][tosa] Add support for MXFP reshape (#207944)
Adds profile compliance support for MXFP reshape.
Commit: 2375505c7c19cf521b9ed5acaf7f359ddd9f216b
https://github.com/llvm/llvm-project/commit/2375505c7c19cf521b9ed5acaf7f359ddd9f216b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/CMakeLists.txt
M llvm/lib/Target/WebAssembly/WebAssembly.h
A llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[NFC][WebAssembly] Move WebAssemblyCoalesceFeaturesAndStripAtomics
Move WebAssemblyCoalesceFeaturesAndStripAtomics to a separate file.
Having a pass implemented directly in the TargetMachine file is a bit
weird.
Reviewers: dschuff, sbc100, aheejin
Pull Request: https://github.com/llvm/llvm-project/pull/209046
Commit: a2b6a1bae7904be696d8283b9bb34331c39a54ef
https://github.com/llvm/llvm-project/commit/a2b6a1bae7904be696d8283b9bb34331c39a54ef
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyCoalesceFeaturesAndStripAtomicsPass
Standard NewPM pass porting.
Reviewers: sbc100, aheejin, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/209054
Commit: 9d28ea2432d4ac2d4f79d5c2a87117a678b74720
https://github.com/llvm/llvm-project/commit/9d28ea2432d4ac2d4f79d5c2a87117a678b74720
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyNullifyDebugValueLists.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyNullifyDebugValueListsPass
Standard NewPM pass porting.
Reviewers: sbc100, aheejin, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/209055
Commit: 66766179575d3193139df7f0c9fc36c414cc84c6
https://github.com/llvm/llvm-project/commit/66766179575d3193139df7f0c9fc36c414cc84c6
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyFixIrreducibleControlFlowPass
Standard NewPM pass porting.
Reviewers: aheejin, sbc100, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/209077
Commit: 8bc9dae5c79d418ee96d920eef9a858f58e71530
https://github.com/llvm/llvm-project/commit/8bc9dae5c79d418ee96d920eef9a858f58e71530
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyArgumentMove.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyArgumentMovePass
Standard NewPM pass porting.
Reviewers: aheejin, sbc100, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/209368
Commit: 543e714713566ca08c2701973f2c1eafb9757b1a
https://github.com/llvm/llvm-project/commit/543e714713566ca08c2701973f2c1eafb9757b1a
Author: David Young <davidayoung at meta.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[lldb][bazel] Add the lldb-mcp binary to the Bazel overlay (#209498)
#143628 added the lldb-mcp tool (an MCP server multiplexer for LLDB),
built by lldb/tools/lldb-mcp/CMakeLists.txt. The Bazel overlay already
models the ProtocolMCP library and the MCP protocol-server plugin, but
not the lldb-mcp executable itself, so it is missing from the Bazel
build.
Add an lldb-mcp cc_binary modeled on the existing lldb-dap target: glob
tools/lldb-mcp/**, expand the macOS Info.plist via expand_template, and
depend on liblldb.wrapper, Host, Utility, ProtocolMCP, and the LLVM
Option/Support libraries. lldb-mcp has no Options.td, so unlike lldb-dap
no gentbl_cc_library is needed.
This properly translates into BUCk internally at Meta and then builds
with buck2, but I cannot validate the bazel build of this new target
directly.
bazel rule generation assisted with: claude
Commit: 426a44a7780c72e523e29218ec89155f97bf5c78
https://github.com/llvm/llvm-project/commit/426a44a7780c72e523e29218ec89155f97bf5c78
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
R clang/test/AST/HLSL/Texture2D-AST.hlsl
R clang/test/AST/HLSL/Texture2D-scalar-AST.hlsl
R clang/test/AST/HLSL/Texture2D-shorthand-AST.hlsl
R clang/test/AST/HLSL/Texture2D-vector-AST.hlsl
R clang/test/AST/HLSL/Texture2DArray-scalar-AST.hlsl
R clang/test/AST/HLSL/Texture2DArray-shorthand-AST.hlsl
R clang/test/AST/HLSL/Texture2DArray-vector-AST.hlsl
A clang/test/AST/HLSL/Textures-AST.hlsl
A clang/test/AST/HLSL/Textures-scalar-AST.hlsl
A clang/test/AST/HLSL/Textures-shorthand-AST.hlsl
A clang/test/AST/HLSL/Textures-vector-AST.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-CalculateLevelOfDetail.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Gather.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-GetDimensions.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Load.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Mips.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Sample.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleBias.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleCmp.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleCmpLevelZero.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleGrad.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleLevel.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Subscript.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-default-explicit-binding.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-default.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-shorthand-contexts.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-CalculateLevelOfDetail.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Gather.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Load.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Mips.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Sample.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleBias.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleCmp.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleCmpLevelZero.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleGrad.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleLevel.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Subscript.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-default-explicit-binding.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-default.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-shorthand-contexts.hlsl
A clang/test/CodeGenHLSL/resources/Textures-CalculateLevelOfDetail.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Gather.hlsl
A clang/test/CodeGenHLSL/resources/Textures-GetDimensions.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Load.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Mips.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Sample.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleBias.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleCmp.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleCmpLevelZero.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleGrad.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleLevel.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Subscript.hlsl
A clang/test/CodeGenHLSL/resources/Textures-default-explicit-binding.hlsl
A clang/test/CodeGenHLSL/resources/Textures-default.hlsl
A clang/test/CodeGenHLSL/resources/Textures-shorthand-contexts.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-CalculateLevelOfDetail.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-GetDimensions.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-Load-errors.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleBias.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleCmp.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleCmpLevelZero.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleGrad.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleLevel.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-Sema.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-Subscript.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-CalculateLevelOfDetail.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-GetDimensions.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleBias.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleCmp.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleCmpLevelZero.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleGrad.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleLevel.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-Sema.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-Subscript.hlsl
A clang/test/SemaHLSL/Resources/Textures-CalculateLevelOfDetail.hlsl
A clang/test/SemaHLSL/Resources/Textures-GetDimensions.hlsl
A clang/test/SemaHLSL/Resources/Textures-Load-errors.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleBias.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleCmp.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleCmpLevelZero.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleGrad.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleLevel.hlsl
A clang/test/SemaHLSL/Resources/Textures-Sema.hlsl
A clang/test/SemaHLSL/Resources/Textures-Subscript.hlsl
R clang/test/SemaHLSL/Texture2D-Gather.hlsl
R clang/test/SemaHLSL/Texture2D-GatherCmp-Vulkan.hlsl
R clang/test/SemaHLSL/Texture2D-mips-errors.hlsl
R clang/test/SemaHLSL/Texture2DArray-Gather.hlsl
R clang/test/SemaHLSL/Texture2DArray-GatherCmp-Vulkan.hlsl
R clang/test/SemaHLSL/Texture2DArray-mips-errors.hlsl
A clang/test/SemaHLSL/Textures-Gather.hlsl
A clang/test/SemaHLSL/Textures-GatherCmp-Vulkan.hlsl
A clang/test/SemaHLSL/Textures-mips-errors.hlsl
Log Message:
-----------
[HLSL] Consolidate texture tests (#209348)
Fixes #205878
This PR consolidates all the current texture tests into files that all
texture types can extend by adding new RUN lines.
This should greatly reduce the amount of effort required to implement
and review tests for new texture types.
Assisted by: Claude Opus 4.8
Commit: 43394198cf089eb054c25e141ddb293f502f9948
https://github.com/llvm/llvm-project/commit/43394198cf089eb054c25e141ddb293f502f9948
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel][libc] Add missing header deps (#209767)
For stat/ioctl/size headers
Not sure which commit exactly broke this, maybe #209449
Commit: 469794e66f86f11ae50015f6199179ca83efc58b
https://github.com/llvm/llvm-project/commit/469794e66f86f11ae50015f6199179ca83efc58b
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/MPI-Checker/MPIFunctionClassifier.cpp
M clang/test/Analysis/MPIMock.h
M clang/test/Analysis/mpichecker.cpp
Log Message:
-----------
[analyzer] Recognize missing MPI collectives in MPI-Checker (#209263)
Fixes a false positive in the `optin.mpi.MPI-Checker` where legitimate
code was flagged with "Request 'X' has no matching nonblocking call."
Background for reviewers unfamiliar with MPI or this checker
------------------------------------------------------------
MPI (Message Passing Interface) is the standard API for communication
between processes in HPC/cluster programs (C/C++/Fortran). Many MPI
operations come in a *nonblocking* form, prefixed with "I" (for
"immediate"): e.g. `MPI_Isend`, `MPI_Iscatter`. A nonblocking call
returns immediately and hands back an `MPI_Request` handle; the caller
must later complete it with `MPI_Wait` (or `MPI_Waitall`). Forgetting to
wait, or reusing a request before waiting, are real bugs (buffer reuse
races, leaked requests).
The MPI-Checker (originally contributed as a GSoC 2016 project, and is a
domain-specific check - hence it's in "optin").
It tracks each `MPI_Request` region through a small state machine and
reports: three misuse patterns:
* **missing wait**: a nonblocking call whose request is never waited on
* **double nonblocking**: a request reused by a second nonblocking call
before being waited on
* **unmatched wait**: `MPI_Wait` on a request with no originating
nonblocking call
Root cause
----------
`MPIFunctionClassifier` maintains a hand-written list of known MPI
functions. That list was incomplete: several standard collectives --
notably the vector variants (`MPI_Iscatterv`, `MPI_Igatherv`, ...), the
scans, the reduce-scatter family, and `MPI_Ibarrier` -- were entirely
absent. Because `isNonBlockingType()` returned `false` for them,
`checkDoubleNonblocking()` never recorded the request as Nonblocking, so
the matching `MPI_Wait` looked unmatched and produced a FP.
Note that only
`isNonBlockingType()`/`isWaitType()`/`isMPI_Wait()`/`isMPI_Waitall()`
actually drive the checker; the per-shape predicates (`isScatterType`,
`isGatherType`, `isCollToColl`, etc.) and their backing containers are
currently unused. `checkDoubleNonblocking()` also reads the request from
the *last* argument, which is generic since every nonblocking MPI
function places `MPI_Request*` last -- so no per-function argument
handling is needed.
Fix
---
Register the remaining standard collectives and mark the nonblocking
("I") variants as nonblocking:
* **vector variants**: `MPI_Scatterv`/`Iscatterv`,
`MPI_Gatherv`/`Igatherv`, `MPI_Allgatherv`/`Iallgatherv`,
`MPI_Alltoallv`/`Ialltoallv`, `MPI_Alltoallw`/`Ialltoallw`
* **nonblocking barrier**: `MPI_Ibarrier`
* **scans**: `MPI_Scan`/`Iscan`, `MPI_Exscan`/`Iexscan`
* **reduce-scatter**: `MPI_Reduce_scatter`/`Ireduce_scatter`,
`MPI_Reduce_scatter_block`/`Ireduce_scatter_block`
These functions are not referenced by any per-shape predicate, so they
are added directly to the classification containers without a dedicated
`IdentifierInfo` member. Neighborhood collectives (`MPI_Ineighbor_*`)
and the wait-family beyond `Wait`/`Waitall`
(`Waitany`/`Waitsome`/`Test*`) remain out of scope.
Adds regression tests covering the reported repro (no warning), and
confirms double-nonblocking and missing-wait are still detected for the
new functions.
Fixes #208107
---------
Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>
Commit: 00f263b209a834eca2092d4a91d25b5413caea39
https://github.com/llvm/llvm-project/commit/00f263b209a834eca2092d4a91d25b5413caea39
Author: Marcos Maronas <mmaronas at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/test/Driver/spirv-amd-toolchain.c
Log Message:
-----------
[HIP][SPIR-V] Enable -spirv-preserve-auxdata (#209520)
Function attributes such as `convergent` are only kept through SPIRV if
`-spirv-preserve-auxdata` is enabled. This is important to keep the
translation as accurate as possible. Also, this aligns with the
translator path.
Commit: 0d6013c30572faddfb03d165cfb33f658c313716
https://github.com/llvm/llvm-project/commit/0d6013c30572faddfb03d165cfb33f658c313716
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-store-s16-true16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-s16-true16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-strict_fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap-gfx11.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (44) (#209734)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 957b6635060d85200d985797eaac8c4dccfd8825
https://github.com/llvm/llvm-project/commit/957b6635060d85200d985797eaac8c4dccfd8825
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.p1.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.live.mask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mul24.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.integer-minmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.strictwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (45) (#209753)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: f8f37a65d472e65561994fb7ae55f6b539c357d4
https://github.com/llvm/llvm-project/commit/f8f37a65d472e65561994fb7ae55f6b539c357d4
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
A mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-barrier-gang-private-init.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-launch-mapping.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-predicate-region-reuse-barrier.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-predicate-region.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-private-local-gang-redundant.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-privatize-local.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-privatize-routine-seq.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-privatize-threadprivate.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-array-shared.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-array.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-block-combine-no-reload.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-combine-region-private-dest.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reuse-barrier-sibling-region-privatize.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-routine-call-nested-if.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-routine-worker-call-with-thread-y-reduction.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-private-dynamic-nw.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-vector-reuse-barrier.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-vector-subgroup-align.mlir
Log Message:
-----------
[mlir][acc] Introduce acc to gpu codegen pass (#209606)
Introduce pass that lowers `acc.compute_region` to the GPU dialect. For
host-side kernels it wraps the region in `gpu.launch`; for specialized
ACC routines already inside a `gpu.func`, the body is lowered in place.
The pass maps nested `scf.parallel` / `scf.for` loops carrying
`acc.par_dims` to GPU block and thread parallelism, materializes
privatization and reductions for the device, and handles
synchronization.
Example input IR:
```
func.func @two_sibling_loops() {
%c4 = arith.constant 4 : index
%c32 = arith.constant 32 : index
%grid = acc.par_width %c4 {par_dim = #acc.par_dim<block_x>}
%block = acc.par_width %c32 {par_dim = #acc.par_dim<thread_x>}
acc.kernel_environment {
%priv = acc.privatize [#acc<par_dims[block_x]>] : () ->
!acc.private_type<memref<32xi32>>
acc.compute_region launch(%g = %grid, %t = %block) ins(%p = %priv)
: (!acc.private_type<memref<32xi32>>) {
%slot = acc.private_local %p : (!acc.private_type<memref<32xi32>>)
-> memref<32xi32>
%c0 = arith.constant 0 : index
%c1 = arith.constant 1 : index
%c32_len = arith.constant 32 : index
scf.parallel (%tx) = (%c0) to (%t) step (%c1) {
scf.parallel (%i) = (%c0) to (%c32_len) step (%c1) {
%v = arith.index_cast %i : index to i32
memref.store %v, %slot[%i] : memref<32xi32>
scf.reduce
} {acc.par_dims = #acc<par_dims[sequential]>}
scf.reduce
} {acc.par_dims = #acc<par_dims[thread_x]>}
scf.parallel (%bx) = (%c0) to (%g) step (%c1) {
scf.parallel (%tx2) = (%c0) to (%t) step (%c1) {
scf.parallel (%j) = (%c0) to (%c32_len) step (%c1) {
%loaded = memref.load %slot[%j] : memref<32xi32>
memref.store %loaded, %slot[%j] : memref<32xi32>
scf.reduce
} {acc.par_dims = #acc<par_dims[sequential]>}
scf.reduce
} {acc.par_dims = #acc<par_dims[thread_x]>}
scf.reduce
} {acc.par_dims = #acc<par_dims[block_x]>}
acc.yield
} {origin = "acc.parallel"}
}
return
}
```
Output IR:
```
module {
func.func @two_sibling_loops() {
%c4 = arith.constant 4 : index
%c32 = arith.constant 32 : index
acc.kernel_environment {
%0 = acc.privatize [#acc<par_dims[block_x]>] : () ->
!acc.private_type<memref<32xi32>>
%c1 = arith.constant 1 : index
gpu.launch blocks(%arg0, %arg1, %arg2) in (%arg6 = %c4, %arg7 =
%c1, %arg8 = %c1)
threads(%arg3, %arg4, %arg5) in (%arg9 = %c32, %arg10
= %c1, %arg11 = %c1) {
%grid_dim_x = gpu.grid_dim x
%grid_dim_y = gpu.grid_dim y
%grid_dim_z = gpu.grid_dim z
%block_dim_x = gpu.block_dim x
%block_dim_y = gpu.block_dim y
%block_dim_z = gpu.block_dim z
%1 = acc.gpu_shared_memory {num_copies = 1 : i64,
static_upper_bound_bytes = 128 : i64}
: () -> memref<32xi32, #gpu.address_space<workgroup>>
%memspacecast = memref.memory_space_cast %1
: memref<32xi32, #gpu.address_space<workgroup>> to
memref<32xi32>
%c0 = arith.constant 0 : index
%c1_0 = arith.constant 1 : index
%c32_1 = arith.constant 32 : index
scf.parallel (%arg12) = (%c0) to (%c32_1) step (%c1_0) {
%2 = arith.index_cast %arg12 : index to i32
memref.store %2, %memspacecast[%arg12] : memref<32xi32>
scf.reduce
} {acc.par_dims = #acc<par_dims[sequential]>}
gpu.barrier
scf.parallel (%arg12) = (%c0) to (%c32_1) step (%c1_0) {
%2 = memref.load %memspacecast[%arg12] : memref<32xi32>
memref.store %2, %memspacecast[%arg12] : memref<32xi32>
scf.reduce
} {acc.par_dims = #acc<par_dims[sequential]>}
gpu.barrier
gpu.terminator
}
}
return
}
}
```
---------
Co-authored-by: Matsu <kmatsumura at nvidia.com>
Commit: f829df1bf55e674aad2d90390b7b53dd141c2c8b
https://github.com/llvm/llvm-project/commit/f829df1bf55e674aad2d90390b7b53dd141c2c8b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant32bit.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-legalize-range-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer-wrong-insert-point.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-cse-nonlocal-convergent-instrs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-legalize-atomic.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-buildvector-identities.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-trunc-bitcast-buildvector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-unmerge-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-load-and-mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-fptrunc_fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-redundant-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-sext_inreg-to-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-shuffle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (46) (#209754)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 703e9b3b79f1520d05fceebabfacf31af4ad4e14
https://github.com/llvm/llvm-project/commit/703e9b3b79f1520d05fceebabfacf31af4ad4e14
Author: Phoebe Linck <phoebe.linck at hpe.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
R flang/test/Lower/OpenMP/Todo/taskwait-depend.f90
A flang/test/Lower/OpenMP/taskwait-depend.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-taskwait-depend.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[Flang][OpenMP] Implement DEPEND clause for TASKWAIT directive (#193568)
Implements support for the `DEPEND` clause on `TASKWAIT`, added in
OpenMP 5.0.
Commit: f1cb3d330c03827247468b4c0437e86ad0b286ad
https://github.com/llvm/llvm-project/commit/f1cb3d330c03827247468b4c0437e86ad0b286ad
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (47) (#209755)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: c78147a9198c45ac1020dfc1d5524d158470309e
https://github.com/llvm/llvm-project/commit/c78147a9198c45ac1020dfc1d5524d158470309e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-merge.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-merge-values-build-vector-s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shader-epilogs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-divergent-addr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-uniform-addr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (48) (#209756)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 649466a54f920970e99574d0d982b8ed35465c8f
https://github.com/llvm/llvm-project/commit/649466a54f920970e99574d0d982b8ed35465c8f
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
Log Message:
-----------
[NFC][OpenACC] fix doc formatting for reduction ops (#209739)
Was not printing correctly due to the matching `$`
Commit: 1725c53752c84cc19c656413b0e75e1dbe9e154b
https://github.com/llvm/llvm-project/commit/1725c53752c84cc19c656413b0e75e1dbe9e154b
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGAttributes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-block-redundant.mlir
Log Message:
-----------
[mlir][acc] Add attribute for redundant execution marking (#209784)
Adds `acc.gpu_block_redundant` attribute for correct gang-redundant
lowering.
OpenACC gang-redundant regions execute on every gang rather than
partitioning work across gangs. When lowering to the GPU dialect, such
regions must not be assigned block-level par dims; only thread-level
parallelism applies. This marks loops with this attribute to ensure
proper execution and to avoid incorrect predication.
Co-authored-by: Delaram Talaashrafi <dtalaashrafi at nvidia.com>
Commit: 15a20079696696162af6aa532bd95f8cd010aaa5
https://github.com/llvm/llvm-project/commit/15a20079696696162af6aa532bd95f8cd010aaa5
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN sqrt builtins (#197342)
Adds codegen for the following AMDGCN square root builtins:
- __builtin_amdgcn_sqrt (double)
- __builtin_amdgcn_sqrtf (float)
- __builtin_amdgcn_sqrth (half)
- __builtin_amdgcn_sqrt_bf16 (bfloat16)
These are lowered to the corresponding `llvm.amdgcn.sqrt` intrinsic calls.
Commit: 35182ec363a6943bd4c6c4158b0de17f7799b6b7
https://github.com/llvm/llvm-project/commit/35182ec363a6943bd4c6c4158b0de17f7799b6b7
Author: David Young <davidayoung at meta.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[lldb][bazel] Add PlatformWasm plugin library to the Bazel overlay (#209749)
Adds the PluginPlatformWasm cc_library plus its PlatformWasmProperties
gentbl_cc_library (settings .td, modeled on PlatformQemuUserProperties)
to the lldb Bazel overlay. Deps mirror
source/Plugins/Platform/WebAssembly/CMakeLists.txt (lldbCore, lldbHost,
lldbTarget, lldbUtility, Support) plus the :PluginPlatformGDB and
:PluginProcessWasm plugin deps its GDB-remote/Web-Inspector sources use.
The library is intentionally left out of DEFAULT_PLUGINS.
bazel rule assisted with: claude
Can confirm this library will convert to BUCK internally at Meta and
build with buck2 where we do have in the default plugin list. I left it
out here, unless there's a desire to add it in.
Commit: 78c8cf7ef90cb0bca766d07a221977fbe2a2a69f
https://github.com/llvm/llvm-project/commit/78c8cf7ef90cb0bca766d07a221977fbe2a2a69f
Author: David Young <davidayoung at meta.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[lldb][bazel] Add ObjectFileXCOFF plugin library to the Bazel overlay (#209747)
Adds the PluginObjectFileXCOFF cc_library to the lldb Bazel overlay,
modeled on PluginObjectFileELF/PluginObjectFileCOFF and mirroring
source/Plugins/ObjectFile/XCOFF/CMakeLists.txt (lldbCore, lldbHost,
lldbSymbol, lldbTarget; llvm BinaryFormat/Object/Support). The library
is intentionally left out of DEFAULT_PLUGINS.
bazel rule assisted with: claude
Can confirm this library will convert to BUCK internally at Meta and
build with buck2 where we do have in the default plugin list. I left it
out here, unless there's a desire to add it in.
Commit: 6526c5ba127123f2c81b21b3f27bfa69dd623f9e
https://github.com/llvm/llvm-project/commit/6526c5ba127123f2c81b21b3f27bfa69dd623f9e
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdivrem24.ll
M llvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
M llvm/test/CodeGen/AMDGPU/udivrem64.r600.ll
Log Message:
-----------
[AMDGPU] Avoid errors with 24-bit div/rem (#209711)
Avoid errors when using floating-point reciprocal to calculate Y/X when
Y = (0x7FFFFF/X)*X-1. Limit expansion to 23-bit signed and 22-bit
unsigned to avoid this issue.
This change is analogous to the change done in
https://github.com/llvm/llvm-project/pull/202753, but in
AMDGPUISelLowering.cpp.
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 4b415b168494b2cbf814db3305ec236aae1562c6
https://github.com/llvm/llvm-project/commit/4b415b168494b2cbf814db3305ec236aae1562c6
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChain.cpp
A clang/test/Driver/Inputs/resource_dir_with_amdgpu_per_target_subdir/lib/amdgpu-amd-amdhsa/libclang_rt.profile.a
M clang/test/Driver/amdgpu-toolchain.c
Log Message:
-----------
[Clang][AMDGPU] Search both amdgcn and amdgpu libraries (#209770)
Summary:
Temporary workaround as we transition triples from amdgcn to amdgpu.
Commit: 2cd090afbe1eddfe8f781d5ccae391e1f69e8ee4
https://github.com/llvm/llvm-project/commit/2cd090afbe1eddfe8f781d5ccae391e1f69e8ee4
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/cmake/base-config-ix.cmake
M compiler-rt/cmake/builtin-config-ix.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Fix amdgcn -> amdgpu conversion for compiler-rt (#209765)
Summary:
We are apparently transitioning to using `amdgpu` everywhere, so these
need to be updated.
Commit: 4279d524cc78d0bac294bb29257c62665121d9f1
https://github.com/llvm/llvm-project/commit/4279d524cc78d0bac294bb29257c62665121d9f1
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
A llvm/test/CodeGen/AMDGPU/vgpr-setreg-pred-block.mir
Log Message:
-----------
[AMDGPU][CodeGen] Place `S_NOP` after `S_SETREG_IMM32_B32` in predecessor MBB (#209620)
When placing a `S_SET_VGPR_MSB` at the beginning of a block, check
whether there exists a `S_SETREG_IMM32_B32(MODE)` in the predecessor
block that falls-through into it; if there is one a `S_NOP` has to be
inserted in between them.
Commit: ea9175f63571dda7efbdbeff9b6eed33879307ac
https://github.com/llvm/llvm-project/commit/ea9175f63571dda7efbdbeff9b6eed33879307ac
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
Log Message:
-----------
Revert "[SLP] Support memory runtime alias checks"
This reverts commit 96a53b1c5356754b4708c0fee8517fd0d69cb1fd to fix
buildbots https://lab.llvm.org/buildbot/#/builders/223/builds/7209
reported in https://github.com/llvm/llvm-project/pull/209305?email_source=notifications&email_token=ABI45DXMMB4TIQHXXWA6NYD5E57EVA5CNFSNUABFM5UWIORPF5TWS5BNNB2WEL2JONZXKZKDN5WW2ZLOOQXTIOJYGA4TIMZVGU3KM4TFMFZW63VMON2GC5DFL5RWQYLOM5S2KZLWMVXHJLDGN5XXIZLSL5RWY2LDNM#issuecomment-4980943556
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209793
Commit: 6352d8437c41915ebdb03537660f3bb48a1bc02a
https://github.com/llvm/llvm-project/commit/6352d8437c41915ebdb03537660f3bb48a1bc02a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (49) (#209757)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 7d638b4dbcb10c224741cdd4634a768c7bc6d305
https://github.com/llvm/llvm-project/commit/7d638b4dbcb10c224741cdd4634a768c7bc6d305
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll
M llvm/test/CodeGen/AMDGPU/add_i128.ll
M llvm/test/CodeGen/AMDGPU/add_i64.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll
M llvm/test/CodeGen/AMDGPU/alignbit-pat.ll
M llvm/test/CodeGen/AMDGPU/allow-check.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll
M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll
M llvm/test/CodeGen/AMDGPU/barrier-elimination.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-uniformity.ll
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
M llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
M llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
M llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/commute_modifiers.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
M llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
M llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
M llvm/test/CodeGen/AMDGPU/cttz-elts.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
M llvm/test/CodeGen/AMDGPU/debug-value2.ll
M llvm/test/CodeGen/AMDGPU/debug_frame.ll
M llvm/test/CodeGen/AMDGPU/default_amdhsa_code_object_version.ll
M llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll
M llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll
M llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
M llvm/test/CodeGen/AMDGPU/extload-align.ll
M llvm/test/CodeGen/AMDGPU/extract-load-i1.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
M llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
M llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
M llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll
M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
M llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir
M llvm/test/CodeGen/AMDGPU/fold-over-exec.mir
M llvm/test/CodeGen/AMDGPU/fold-readlane.mir
M llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll
M llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll
M llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
M llvm/test/CodeGen/AMDGPU/freeze-other-uses-issue-198094.ll
M llvm/test/CodeGen/AMDGPU/global-alias.ll
M llvm/test/CodeGen/AMDGPU/hoist-cond.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-deduced-arg-attr.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll
M llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir
M llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll
M llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
M llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
M llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
M llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (50) (#209776)
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 5699900ae02272a558761b6de3f18a790abe763f
https://github.com/llvm/llvm-project/commit/5699900ae02272a558761b6de3f18a790abe763f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/AST/ByteCode/virtual-bases.cpp
Log Message:
-----------
[clang][bytecode] Fix virtual-bases.cpp on 32 bit hosts (#209766)
It currently fails on clang-armv8-quick with:
```console
# | error: diagnostics with 'error' severity seen but not expected:
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 441: static assertion failed due to requirement '((__builtin_constant_p((char *)&c.c) ? ((char *)&c.c) : ((char *)&c.c)) - (__builtin_constant_p((char *)&c) ? ((char *)&c) : ((char *)&c))) == 12'
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 442: static assertion failed due to requirement '((__builtin_constant_p((char *)&c.b) ? ((char *)&c.b) : ((char *)&c.b)) - (__builtin_constant_p((char *)&c) ? ((char *)&c) : ((char *)&c))) == 8'
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 443: static assertion failed due to requirement '((__builtin_constant_p((char *)&c.a) ? ((char *)&c.a) : ((char *)&c.a)) - (__builtin_constant_p((char *)&c) ? ((char *)&c) : ((char *)&c))) == 20'
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 444: static assertion failed due to requirement '((__builtin_constant_p((char *)&c.x) ? ((char *)&c.x) : ((char *)&c.x)) - (__builtin_constant_p((char *)&c) ? ((char *)&c) : ((char *)&c))) == 16'
# | error: diagnostics with 'note' severity seen but not expected:
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 441: expression evaluates to '8 == 12'
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 442: expression evaluates to '4 == 8'
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 443: expression evaluates to '16 == 20'
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 444: expression evaluates to '12 == 16'
# | 8 errors generated.
```
Commit: 0429183bd83dee21b7e074160e241129ca1cde25
https://github.com/llvm/llvm-project/commit/0429183bd83dee21b7e074160e241129ca1cde25
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
Log Message:
-----------
[gn build] Port 2375505c7c19 (#209797)
Commit: 21db8e9e2ad0ba161d5939de39119951c61e64ec
https://github.com/llvm/llvm-project/commit/21db8e9e2ad0ba161d5939de39119951c61e64ec
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
Log Message:
-----------
[gn build] Port 9a4deccf90ae (#209799)
Commit: bfc2d553401bfd69c57f848d35d5ec5952298cbb
https://github.com/llvm/llvm-project/commit/bfc2d553401bfd69c57f848d35d5ec5952298cbb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll
M llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll
M llvm/test/CodeGen/AMDGPU/lds-alignment.ll
M llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
M llvm/test/CodeGen/AMDGPU/lds-size.ll
M llvm/test/CodeGen/AMDGPU/liveness.mir
M llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir
M llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll
M llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
M llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
M llvm/test/CodeGen/AMDGPU/madmk.ll
M llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir
M llvm/test/CodeGen/AMDGPU/mem-builtins.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-m0.mir
M llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
M llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir
M llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
M llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
M llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
M llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/nullptr.ll
M llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
M llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
M llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll
M llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir
M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
M llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
M llvm/test/CodeGen/AMDGPU/rcp_iflag.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll
M llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir
M llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
M llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
M llvm/test/CodeGen/AMDGPU/register-count-comments.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir
M llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
M llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll
M llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select-opt.ll
M llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
M llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/setcc-select.ll
M llvm/test/CodeGen/AMDGPU/setcc-sext.ll
M llvm/test/CodeGen/AMDGPU/setcc.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir
M llvm/test/CodeGen/AMDGPU/sgprcopies.ll
M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/si-i1-copies.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (51) (#209777)
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: ff58fb1cef69c6d9e2e8889f2e72b962858a5475
https://github.com/llvm/llvm-project/commit/ff58fb1cef69c6d9e2e8889f2e72b962858a5475
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
M llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll
M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
M llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
M llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
M llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
M llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir
M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
M llvm/test/CodeGen/AMDGPU/subreg_interference.mir
M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
M llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
M llvm/test/CodeGen/AMDGPU/verify-sop.mir
M llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir
M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-debug-non-first-terminators.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir
M llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll
M llvm/test/CodeGen/AMDGPU/zext-lid.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (52) (#209778)
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 4596278ca49b13280176c6ae25ab673772185d56
https://github.com/llvm/llvm-project/commit/4596278ca49b13280176c6ae25ab673772185d56
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis/BUILD.gn
Log Message:
-----------
[gn build] Port ef118b5b3a61 (#209800)
Commit: d0231d2195976b5b091b8e55f4d4fd2b55875ee5
https://github.com/llvm/llvm-project/commit/d0231d2195976b5b091b8e55f4d4fd2b55875ee5
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i8-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/handle-iptr-with-data-layout-to-not-assert.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-01uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i32-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i64-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll
Log Message:
-----------
[LV] Fix LoopVectorize/X86/CostModel tests when regenerated with UTC. NFC (#209802)
Some of the cost model tests were passing, but their UTC arguments
were outdated and CHECK lines disappeared when regenerating them.
- Add additional --filter lines for VPlan cost model CHECK lines,
which were manually written previously
- Update the --filter argument for the updated INTERLEAVE-GROUP print
output
- Regenerate strided-load-*.ll tests with UTC
- Pass -vplan-print-metadata=false for tests that were using
hand-written regexes in CHECK lines
Commit: ee08b1c5553cd558458b9570646038b9422ca397
https://github.com/llvm/llvm-project/commit/ee08b1c5553cd558458b9570646038b9422ca397
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memsetinline.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (53) (#209779)
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 42c2980c7c632d7a45776d3e2c51627100f6e763
https://github.com/llvm/llvm-project/commit/42c2980c7c632d7a45776d3e2c51627100f6e763
Author: 陈子昂 <2802328816 at qq.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
A llvm/test/Transforms/LoopUnroll/full-unroll-scev-invalidation.ll
Log Message:
-----------
[LoopUnroll] Invalidate SCEV after full unrolling (#208874)
Full unrolling may leave stale ScalarEvolution loop and disposition
caches around the loop pass boundary. A later IndVars pass can then use
stale exit count information and incorrectly fold reachable exits.
Invalidate SCEV loop and disposition caches after successful full
unrolling before preserving `ScalarEvolutionAnalysis.`
Fixes #207744.
Commit: c57f88d5178861974c8bcd61657d87275c835aa5
https://github.com/llvm/llvm-project/commit/c57f88d5178861974c8bcd61657d87275c835aa5
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/check-omp-variant.cpp
M flang/lib/Semantics/openmp-utils.cpp
M flang/test/Semantics/OpenMP/metadirective-loop-applicability.f90
M flang/test/Semantics/OpenMP/metadirective-loop-nest.f90
M flang/unittests/Semantics/OpenMPUtils.cpp
Log Message:
-----------
[flang][OpenMP] Fix metadirective loop semantic checks (#208844)
This is a follow-up to https://github.com/llvm/llvm-project/pull/207088.
Post-merge review feedback:
* Rename mayVariantBeSelected to MayVariantBeSelected and move it to
the shared OpenMP semantic utilities so declare-variant checking can
reuse it.
* Explain why a WHEN selector is recorded only when its modifier list
contains exactly one element.
* Diagnose loop-associated variants that end a declaration-only
program unit, such as a module with no execution part.
Additional correctness fixes:
* Handle consecutive metadirectives and modules or submodules with
contained procedures without silently dropping an earlier
loop-associated variant.
* Prevent a loop-associated variant in an interface, BLOCK construct,
conditional branch, or nested body from being checked against an
unrelated loop outside that scope.
* Avoid false or missing loop diagnostics when match_any or match_none
combines target selectors with user or construct selectors.
Assisted with codex.
Commit: 36dd090234dff6a9059bf9288e4c61ec77a42d82
https://github.com/llvm/llvm-project/commit/36dd090234dff6a9059bf9288e4c61ec77a42d82
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
Log Message:
-----------
[SLP] Support memory runtime alias checks
Vectorize straight-line code blocked by runtime-checkable may-alias
dependencies by versioning the block. Drop the deps, and if the tree is
profitable, emit base-object address-range overlap checks branching to a
vector fast path or an original-order scalar fallback.
Fixes #201534
Original Pull Request: https://github.com/llvm/llvm-project/pull/203631
Recommit after revert in a9ba4d3fd27a05b31adfeaab5dcd42d8e43c1931,
related to late commit before the release and small after-commit change
request
Recommit after revert in ea9175f63571dda7efbdbeff9b6eed33879307ac, fixed
testing with PROFCHECK=ON
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209820
Commit: 816a5eacc4407e091a76d0205a8221ade044f439
https://github.com/llvm/llvm-project/commit/816a5eacc4407e091a76d0205a8221ade044f439
Author: Vineet Kumar <173554+vntkmr at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/include/flang/Evaluate/call.h
M flang/include/flang/Evaluate/fold.h
M flang/include/flang/Evaluate/shape.h
M flang/include/flang/Evaluate/traverse.h
M flang/include/flang/Evaluate/type.h
M flang/include/flang/Semantics/expression.h
M flang/lib/Evaluate/call.cpp
M flang/lib/Evaluate/characteristics.cpp
M flang/lib/Evaluate/fold-implementation.h
M flang/lib/Evaluate/fold.cpp
M flang/lib/Evaluate/formatting.cpp
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/shape.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Evaluate/type.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/expression.cpp
A flang/test/Evaluate/fold-conditional-arg.f90
M flang/test/Semantics/conditional-arg.f90
Log Message:
-----------
[flang] Add semantics support for Fortran 2023 conditional arguments (F2023 R1526-R1528) (#195345)
This PR
- Adds semantic analysis for F2023 conditional arguments (F2023
R1526-R1528), enforcing constraints F2023 C1538-C1545.
- Adds shape handling and folding for conditional args.
- Adds semantic tests.
(More details in commit messages)
This PR does not implement lowering to HLFIR; That will be a separate
PR.
AI use disclaimer: The changes in this PR were substantially
generated with the assistance of AI (claude opus 4.6 via Github
CoPilot). In accordance with the LLVM project’s AI use policy, I have
reviewed and tested the code to the best of my ability.
Commit: f10ede511119d7f31f2c6aaca3cbcb1ea00164ce
https://github.com/llvm/llvm-project/commit/f10ede511119d7f31f2c6aaca3cbcb1ea00164ce
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/examples/python/templates/operating_system.py
M lldb/examples/python/templates/scripted_breakpoint.py
M lldb/examples/python/templates/scripted_frame_provider.py
M lldb/examples/python/templates/scripted_hook.py
M lldb/examples/python/templates/scripted_platform.py
M lldb/examples/python/templates/scripted_process.py
M lldb/examples/python/templates/scripted_thread_plan.py
Log Message:
-----------
[lldb/script] Add type hints to scripted extension base classes (#209680)
This patch adds type annotations to every method (parameters and return
types) and every `self.<name>` attribute of the scripted extension base
classes shipped under `lldb/examples/python/templates/`. Extension
authors reading the base classes -- or an IDE navigating them -- can now
see the `lldb.SB*` contract each method exposes without having to
cross-reference the docstring.
`scripting extension generate` also picks the annotations up: derived
class docstrings advertise each inherited attribute together with its
declared type, and the generated method signatures carry their parameter
and return annotations too.
The classes covered are `ScriptedProcess`, `ScriptedThread`,
`ScriptedFrame`, `PassthroughScriptedProcess`,
`PassthroughScriptedThread`, `ScriptedFrameProvider`,
`ScriptedBreakpointResolver`, `ScriptedThreadPlan`, `ScriptedHook`,
`ScriptedPlatform`, and `OperatingSystem`.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 2c2e43675910603bab1b163655786e4850569d74
https://github.com/llvm/llvm-project/commit/2c2e43675910603bab1b163655786e4850569d74
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/test/SemaTemplate/class-template-spec.cpp
Log Message:
-----------
Create a Template member to be the MemberSpec of a failed TemplVarDecl (#209604)
Patch #200092 changed to no longer check the previous var template when
setting whether the current one is a member specialization. However, if
the previous one was actually an error case (see the example here and in
the report), we ended up trying to do that anyway, which caused an
assertion.
This patch puts in a 'fake' declaration for the not-found declaration after we
emit the 'not found' error for the purposes of allowing our diagnostics to
continue evaluating these without causing problems.
Fixes: #209432
Commit: edea055ee85427ad700e74cfa074d6c5ed5e6d39
https://github.com/llvm/llvm-project/commit/edea055ee85427ad700e74cfa074d6c5ed5e6d39
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-constructor.f90
A flang/test/Fir/CUDA/cuda-register-allocator-0.f90
A flang/test/Fir/CUDA/cuda-register-allocator-1.f90
Log Message:
-----------
[flang][cuda] Register allocator only when needed (#208355)
Register allocator only when needed to avoid bringing in symbol when not
strictly needed.
Commit: 67df1e0f664b85c08d4281e465d3502495bfa035
https://github.com/llvm/llvm-project/commit/67df1e0f664b85c08d4281e465d3502495bfa035
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel][mlir][acc] Fix f8f37a65d472e65561994fb7ae55f6b539c357d4 (#209809)
Add missing deps
Commit: bad82c1af5198267f44bba363e20b24dd23d2a24
https://github.com/llvm/llvm-project/commit/bad82c1af5198267f44bba363e20b24dd23d2a24
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[bazel][lldb] Add layering deps (#209813)
Extra deps needed for #209749 and #209747
Commit: a57c590c159c934d3759703a3f773eb09d3ffb09
https://github.com/llvm/llvm-project/commit/a57c590c159c934d3759703a3f773eb09d3ffb09
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/Driver/openmp-invalid-target-id.c
Log Message:
-----------
[clang][OpenMP][test] Specify libomp flag (#209804)
The test added in #209740 assumes that `-fopenmp=libomp` is the default
value, and does not work when the build is configured w/ `libgomp` as
the default instead.
Commit: 2c57ae5efb0159521287c80255e3a604f3b0dcfe
https://github.com/llvm/llvm-project/commit/2c57ae5efb0159521287c80255e3a604f3b0dcfe
Author: Faijul Amin <md.faijul.amin at intel.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
A llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll
Log Message:
-----------
[SPIRV] Sign-extend operands of sign-sensitive ops on sub-pow2 widths (#203661)
## Problem
Without extensions, `SPIRVPreLegalizer` widens sub-pow2 scalars (`s4`,
`s24`, ...) to the next legal width by relabeling the LLT only — no
sign-extension is inserted. Sign-sensitive ops (signed `G_ICMP`,
`G_ASHR`, `G_SDIV`, `G_SREM`) then read the sign bit at the wrong
position. As a result `icmp slt i4 %x, 0` always returned `false` even
for negative `i4`.
## Fix
- `SPIRVLegalizerInfo.cpp`: declare `G_SEXT_INREG.lower()` so the
legalizer expands it to `(x << k) ashr k`.
- `SPIRVPreLegalizer.cpp`: before the widening loop, emit `G_SEXT_INREG`
on each value operand of a sign-sensitive MI whose original width is
sub-pow2.
## Test
`llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll` covers `icmp
slt`/`ashr`/`sdiv`/`srem` on `i4`, `icmp slt` on `i24`, and negative
cases (`icmp ult`, `lshr`) that must not emit sign-extension shifts
Commit: b61b45f30cb1d7e88a6877080978aa95b83b7f87
https://github.com/llvm/llvm-project/commit/b61b45f30cb1d7e88a6877080978aa95b83b7f87
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/ELF/ELFHeader.cpp
M lldb/source/Plugins/ObjectFile/ELF/ELFHeader.h
Log Message:
-----------
[lldb] Convert ELFSymbol dump methods to use StringRef (#209650)
I'm working on changing how Section stores its own name (currently a
ConstString). I broke this change out into its own small PR because of
the complexity of rewriting the format string in ELFSymbol::Dump.
Commit: e956df27dfaf556f54a96ed22e85f1e16c7a38e3
https://github.com/llvm/llvm-project/commit/e956df27dfaf556f54a96ed22e85f1e16c7a38e3
Author: Markos Horro <marcosh at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/BitVector.h
M llvm/include/llvm/ADT/SmallBitVector.h
M llvm/unittests/ADT/BitVectorTest.cpp
Log Message:
-----------
[LLVM][ADT] Adding range-based test_all and test_any methods for BitVector (#209790)
Commit: 0cf914adef4b0f1f5251354b91f5c709b95b1b1e
https://github.com/llvm/llvm-project/commit/0cf914adef4b0f1f5251354b91f5c709b95b1b1e
Author: Michael Jones <michaelrj at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libcxx/cmake/caches/Generic-llvm-libc.cmake
M libcxx/test/configs/llvm-libc++-llvm-libc.cfg.in
M libcxx/test/libcxx/language.support/support.dynamic/assert.nothrow_new_not_overridden_fno_exceptions.pass.cpp
M libcxx/test/libcxx/language.support/support.dynamic/new_dont_return_nullptr.pass.cpp
M libcxx/test/libcxx/thread/thread.condition/PR30202_notify_from_pthread_created_thread.pass.cpp
M libcxx/test/libcxx/thread/thread.threads/thread.thread.class/thread.thread.member/native_handle.pass.cpp
M libcxx/test/std/depr/depr.c.headers/wchar_h.compile.pass.cpp
M libcxx/test/std/depr/depr.c.headers/wctype_h.compile.pass.cpp
M libcxx/test/std/input.output/syncstream/osyncstream/thread/several_threads.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.member.ops/divide_equal_complex.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.ops/complex_divide_complex.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.ops/scalar_divide_complex.pass.cpp
M libcxx/test/std/numerics/rand/rand.dist/rand.dist.bern/rand.dist.bern.bin/eval.PR44847.pass.cpp
M libcxx/test/std/numerics/rand/rand.dist/rand.dist.bern/rand.dist.bern.bin/io.pass.cpp
M libcxx/test/std/strings/c.strings/cwchar.pass.cpp
M libcxx/test/std/strings/c.strings/cwctype.pass.cpp
M libcxx/test/std/strings/string.conversions/to_wstring.pass.cpp
M libcxx/test/std/thread/thread.condition/notify_all_at_thread_exit_lwg3343.pass.cpp
M libcxx/test/std/thread/thread.threads/thread.thread.this/sleep_for.signals.pass.cpp
M libcxx/test/std/time/time.hash/time.hash_enabled.pass.cpp
M libcxxabi/test/configs/llvm-libc++abi-llvm-libc.cfg.in
Log Message:
-----------
[libcxx][libc] update LLVM-libc test status (#201236)
This update removes some unnecessary carveouts, marks some newly
XFAILing tests, and unmarks some now passing tests.
With this change the status of tests is:
Total Discovered Tests: 11471
Unsupported : 2098 (18.29%)
Passed : 9260 (80.73%)
Expectedly Failed: 113 (0.99%)
Assisted-by: Automated tooling, human reviewed.
Commit: 547e9d0c9175f37c9ddd367bbe443a2fd7d6ab7a
https://github.com/llvm/llvm-project/commit/547e9d0c9175f37c9ddd367bbe443a2fd7d6ab7a
Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M openmp/runtime/src/kmp_barrier.cpp
Log Message:
-----------
[OpenMP] Fix endian bug in hierarchical barrier code (#117073)
The "oncore" flavor of the hierarchical barrier code uses a single
uint64 to hold both a barrier state *and* a set of flags for the current
node's "leaf kids" in the tree.
To make this work, the barrier state is placed in the least-significant
byte of the uint64, and the flags for leaf kids are placed in other
bytes of the uint64 starting from the most-significant byte to represent
the first child.
At least, this is how it works on little-endian systems. On big-endian
hosts, the current code unfortunately places the leaf kid flags starting
from the *least* significant byte of the uint64, where they will overlap
and clobber the barrier state byte, resulting in corrupted barrier
behavior.
To fix this, this PR changes the child flag offsets to always start with
the MSB, on both big- and little- endian hosts. This was complicated a
bit by the following issues:
- The byte offset was stored "off-by-one" for some reason. This makes it
impossible to represent the MSB on big- endian systems (i.e. byte 0,
which would have to be represented by -1 if offset by one, which does
not fit into the uint8 offset field).
Fixed by storing and using the "offset" field as the actual byte number,
not off-by-one.
- The "offset" field was never used for the master node, but it was
still computed. That computed value was also invalid as it pointed
outside the target uint64, but that didn't matter as it was unused. For
big-endian systems, however, the computation would have resulted in a
*negative* value, which again cannot be stored in the uint8 field.
Fixed by skipping the (unused) computation on the master node and
setting the "offset" field to a dummy value.
This is intended to be NFC on little-endian machines.
Commit: 0639fe182414f04d767175a195a8a26da5d48159
https://github.com/llvm/llvm-project/commit/0639fe182414f04d767175a195a8a26da5d48159
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineINSERT_SUBVECTOR - use peekThroughBitcastsAndExtracts helper to match target shuffles as well. NFC. (#209803)
We were always checking if the result of peekThroughBitcastsAndExtracts
was a target shuffle - so let the helper do it for us.
Makes it easier for future handling of faux shuffles as well.
Commit: d55259aa61b703ce63613a022c5cb14f6b588b46
https://github.com/llvm/llvm-project/commit/d55259aa61b703ce63613a022c5cb14f6b588b46
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
M llvm/include/llvm/ADT/GenericUniformityImpl.h
M llvm/include/llvm/ADT/GenericUniformityInfo.h
M llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
M llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
M llvm/lib/Analysis/CFG.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/CodeGen/MachineCycleAnalysis.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
Log Message:
-----------
[CycleInfo] Move representation-dependent queries to GenericCycleInfo. NFC
With the Euler tour representation (#208614), blocks live in
GenericCycleInfo::BlockLayout and GenericCycle keeps a `CI` back-pointer just
so the out-of-line contains(BlockT *) and blocks() can reach it.
Adopt the design suggested by @aengelke, move the
representation-dependent queries to GenericCycleInfo, taking the cycle
as an argument (contains, getBlocks, getExitBlocks, getExitingBlocks,
getCyclePreheader, getCyclePredecessor, verifyCycle, verifyCycleNest,
and per-cycle print), and delete GenericCycle::CI.
- GenericCycleInfo's move operations become defaulted, dropping the
CI re-pointing walk, and sizeof(GenericCycle) shrinks by a pointer.
- isCycleInvariant gains a MachineCycleInfo parameter, and
GenericUniformityInfo gains getCycleInfo() for callers that only hold the
uniformity result.
Aided by Claude Fable 5
Pull Request: https://github.com/llvm/llvm-project/pull/209665
Commit: a16f3a09415d28928b1e5133ad63ad3d2d97fa99
https://github.com/llvm/llvm-project/commit/a16f3a09415d28928b1e5133ad63ad3d2d97fa99
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
A libcxx/test/benchmarks/algorithms/modifying/replace_copy.bench.cpp
Log Message:
-----------
[libc++] Add benchmarks for std::replace_copy and std::replace_copy_if (#207070)
Assisted by Claude
Commit: 0a933be62ea9fb3c6835ffa37852ef9a0288bccf
https://github.com/llvm/llvm-project/commit/0a933be62ea9fb3c6835ffa37852ef9a0288bccf
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
A libcxx/test/benchmarks/algorithms/sorting/binary_search.bench.cpp
A libcxx/test/benchmarks/algorithms/sorting/equal_range.bench.cpp
M libcxx/test/benchmarks/algorithms/sorting/lower_upper_bound.bench.cpp
Log Message:
-----------
[libc++] Add benchmarks for std::binary_search and std::equal_range (#207268)
The found and not-found paths are measured as separate benchmarks. For
equal_range we additionally cover a unique match, a large equal range,
and an absent key.
As a drive-by, add a predicate variation to the existing lower_bound and
upper_bound benchmarks.
Commit: f4120c4a1d0daaac81983df10a809df883b25173
https://github.com/llvm/llvm-project/commit/f4120c4a1d0daaac81983df10a809df883b25173
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libcxx/include/__algorithm/copy_n.h
M libcxx/include/__algorithm/for_each_n.h
M libcxx/include/__algorithm/generate_n.h
M libcxx/include/__algorithm/ranges_for_each_n.h
M libcxx/include/__bit_reference
A libcxx/test/libcxx/algorithms/alg.nonmodifying/alg.foreach/assert.for_each_n.pass.cpp
A libcxx/test/libcxx/algorithms/alg.nonmodifying/alg.foreach/assert.ranges.for_each_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.generate/generate_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.generate/ranges_generate_n.pass.cpp
Log Message:
-----------
[libc++] Treat negative counts in copy_n & friends as no-ops (#207086)
The standard specifies copy_n, fill_n and generate_n (both std and
ranges) to be no-ops when passed a negative count. This patch fixes
libc++ to abide by that requirement, with tests.
It's worth noting that std::for_each_n makes n > 0 a precondition
instead: we add the check and tests for it.
Fixes #193613
Commit: dccdacc2dc49c708a8fde04b04ae76b552aaf122
https://github.com/llvm/llvm-project/commit/dccdacc2dc49c708a8fde04b04ae76b552aaf122
Author: Victor Perez <victor.pc.upm at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Dialect/Arith/canonicalize.mlir
Log Message:
-----------
[mlir][arith] Canonicalize `addf(negf(x), y)` to `subf(y, x)` (#209277)
`arith.addf` had no canonicalization patterns at all. This adds a
canonicalizer rewriting `addf(negf(x), y) -> subf(y, x)` (and the
commuted operand order).
The rewrite is valid under any rounding mode, which is propagated to the
`subf`: `negf` is an exact sign flip, IEEE addition is commutative, and
`y - x` is the correctly rounded `y + (-x)`, so `subf(y, x)` and
`addf(negf(x), y)` are bit-identical for every rounding mode. Fast-math
flags are propagated to the new `subf`.
----
Code partially generated with Claude Code.
Signed-off-by: Víctor Pérez Carrasco <victorperez at fb.com>
Co-authored-by: Víctor Pérez Carrasco <victorperez at fb.com>
Commit: 15cd911154b5712e37187c4507ee7b29c412b998
https://github.com/llvm/llvm-project/commit/15cd911154b5712e37187c4507ee7b29c412b998
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/BPF/sink-min-max.ll
Log Message:
-----------
[BPF] Use UTC for sink-min-max.ll
The assertions were providing a similar level of coverage. Autogenerate
them to make maintenance easier.
Reviewers: mtrofin, yonghong-song, eddyz87
Pull Request: https://github.com/llvm/llvm-project/pull/209681
Commit: c102184cbdcb8467ce1caf384ecd4e36d97fa37c
https://github.com/llvm/llvm-project/commit/c102184cbdcb8467ce1caf384ecd4e36d97fa37c
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
M lld/test/ELF/local-symbols-order.s
M lld/test/ELF/lto/parallel-internalize.ll
M lld/test/ELF/ppc64-local-entry.s
M lld/test/ELF/relocatable-comdat-multiple.s
M lld/test/ELF/relocatable-comdat2.s
M lld/test/ELF/relocatable-discard-locals.s
M lld/test/ELF/relocatable-gc.s
M lld/test/ELF/relocatable.s
M lld/test/ELF/strtab-nodedup.s
Log Message:
-----------
[ELF] Synthesize STT_FILE if necessary (#209087)
lld groups local symbols in .symtab by input file, appending a symbol
converted to STB_LOCAL (hidden visibility, version script `local:`, or
--exclude-libs) to its file's group. The nearest preceding STT_FILE then
claims the symbol, but the attribution can be wrong: the file may
contain multiple STT_FILE symbols (-r output), or lack an STT_FILE for
the symbol's unit.
```
FILE LOCAL DEFAULT ABS a.c
NOTYPE LOCAL DEFAULT 7 a_local
FILE LOCAL DEFAULT ABS b.c
NOTYPE LOCAL DEFAULT 7 b_local
NOTYPE LOCAL DEFAULT 7 a_localized
```
Follow GNU ld:
- If the output contains an STT_FILE symbol, place at the end of the
local part, after a synthetic STT_FILE with an empty name, every local
that cannot be attributed to a file: symbols converted to STB_LOCAL,
linker-synthesized symbols such as `_DYNAMIC`, and range-extension
thunks (parented to the internal file, which has no STT_FILE).
- For -r output, synthesize an STT_FILE named after the input file for
an input that outputs local symbols but no STT_FILE, so that its locals
are not attributed to a preceding file. We use the basename instead of
the full name for local determinism (#47367).
GNU ld synthesizes this per-input STT_FILE for executable and
shared-object output as well. Restrict it to -r for now to minimize test
updates.
Close #47367 and #191478
Commit: 521d3e375ecb81d8b7c2d501496be11bdbd8cec0
https://github.com/llvm/llvm-project/commit/521d3e375ecb81d8b7c2d501496be11bdbd8cec0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
M llvm/test/CodeGen/BPF/sink-min-max.ll
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[BPF][ProfCheck] Fix sink-min-max.ll
In bpf-check-and-opt-ir, llvm.umax and llvm.umin are lowered into
explicit comparisons/i1 bitwise operations involving select. Make sure
to mark the selects as having an explicitly unknown profile given we
cannot infer what is likely/unlikely to avoid profcheck failures.
Reviewers: yonghong-song, mtrofin, eddyz87
Pull Request: https://github.com/llvm/llvm-project/pull/209682
Commit: 7cef6a72a1641cf3841b401782c4434635bf3d73
https://github.com/llvm/llvm-project/commit/7cef6a72a1641cf3841b401782c4434635bf3d73
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
Log Message:
-----------
[CycleInfo] Number cycles and move the exit-block cache to GenericCycleInfo. NFC
Assign each cycle a preorder ID in layoutBlocks's Euler-tour walk and
move the caches into a lazily allocated table indexed by ID, shrinking
sizeof(GenericCycle) from 128 to 80. appendEntry/setSingleEntry no
longer invalidate: the exit-block set does not depend on entries. Delete
the unused GenericCycle::clear.
Aided by Claude Fable 5
Pull Request: https://github.com/llvm/llvm-project/pull/209666
Commit: 50d9b2768f4cf224ed7c3d15703aa2d5190f9b4a
https://github.com/llvm/llvm-project/commit/50d9b2768f4cf224ed7c3d15703aa2d5190f9b4a
Author: Matt <MattPD at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/include/flang/Lower/OpenMP.h
M flang/include/flang/Lower/Support/ReductionProcessor.h
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/mod-file.h
M flang/lib/Semantics/openmp-utils.cpp
A flang/test/Lower/OpenMP/Todo/declare-reduction-allocatable-trivial.f90
R flang/test/Lower/OpenMP/Todo/declare-reduction-operator-multiple-types.f90
R flang/test/Lower/OpenMP/Todo/declare-reduction-operator-use-assoc.f90
R flang/test/Lower/OpenMP/Todo/multiple-types-declare_reduction.f90
M flang/test/Lower/OpenMP/declare-reduction-character-allocatable.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-component.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-defined-assign.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-rhs-call.f90
M flang/test/Lower/OpenMP/declare-reduction-intrinsic-op.f90
A flang/test/Lower/OpenMP/declare-reduction-intrinsic-same-name-different-scope.f90
M flang/test/Lower/OpenMP/declare-reduction-logical-init.f90
A flang/test/Lower/OpenMP/declare-reduction-merge-hermetic.f90
A flang/test/Lower/OpenMP/declare-reduction-merge-version-skew.f90
A flang/test/Lower/OpenMP/declare-reduction-name-type-token-collision.f90
A flang/test/Lower/OpenMP/declare-reduction-named-renamed.f90
A flang/test/Lower/OpenMP/declare-reduction-named-separate-rename.f90
A flang/test/Lower/OpenMP/declare-reduction-named-use-assoc.f90
M flang/test/Lower/OpenMP/declare-reduction-no-initializer-derived.f90
M flang/test/Lower/OpenMP/declare-reduction-no-initializer-intrinsic.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-collide.f90
M flang/test/Lower/OpenMP/declare-reduction-operator-derived.f90
M flang/test/Lower/OpenMP/declare-reduction-operator-host-assoc.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-merged.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-multiple-types.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-renamed.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-collide-unused.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-combiners.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-hermetic.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-intrinsic-all.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-intrinsic-collide.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-intrinsic.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-multitype-partial.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-reexport.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-remerge.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-rename-remerge.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-submodule.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-unused-unsupported.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-use-assoc.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-use-only-nonreduction.f90
M flang/test/Lower/OpenMP/declare-reduction-operator.f90
M flang/test/Lower/OpenMP/declare-reduction-same-name-different-scope.f90
A flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic-multiple-types.f90
A flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic-separate.f90
A flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic-use-assoc.f90
M flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic.f90
A flang/test/Lower/OpenMP/declare-reduction-special-separate-reexport.f90
M flang/test/Lower/OpenMP/declare-reduction-target-intrinsic.f90
A flang/test/Lower/OpenMP/multiple-types-declare_reduction.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-combsub.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-derivedtype.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-initsub.f90
M flang/test/Lower/OpenMP/omp-declare-reduction.f90
A flang/test/Semantics/OpenMP/declare-reduction-ambiguous.f90
Log Message:
-----------
[flang][OpenMP] Lower cross-module user-defined declare reduction (#207493)
Lower a reduction clause naming a USE-associated, renamed, or merged-generic
user-defined reduction, which currently aborts lowering with a "not yet
implemented" TODO. Semantics already accepts these programs (since #200329).
This covers the defined-operator, intrinsic-operator, and named forms, each for
one or several types in a single declare reduction. One shape is still deferred.
A reduction on an allocatable or pointer operand of a trivial intrinsic element
type (integer, real, complex, or logical) is not lowered yet and reaches a clean
TODO, tracked by #186765. Character and derived-type allocatable reductions do
lower.
Fixes #207255.
Fixes #207489.
An imported reduction is materialized lazily. Its `omp.declare_reduction` op is
created on demand, only when a reduction clause has resolved the exact reduction
it references, through the same lowering path a local declare reduction uses.
There is no separate eager pass that walks accessible scopes to pre-create ops.
The module only-list property is therefore structural. A program using
`use m, only: <non-reduction>` never emits m's reduction, because nothing
references it. One path handles every import form: plain and renamed USE, nested
and merged generic operators, submodules, and intrinsic operators.
Resolve the use-site reduction to its source symbol through the shared semantic
resolver (`Fortran::semantics::omp::FindUserReductionSymbol`), extracted from
check-omp-structure.cpp into Semantics/openmp-utils so lowering and the semantic
checks share one resolution authority. Name the op from the resolved symbol's
ultimate name and owning scope via `getScopedUserReductionName`, on both the
clause and directive sides so the two cannot drift.
For a multi-type declare reduction, the same-file directive emits one op per
listed type and binds each variable to the op for its type. Lazy materialization
is stricter, emitting only the per-type op a clause requests, so an unsupported
sibling type does not block a supported one. The per-type lists advance in
lockstep: type, combiner, and initializer. The type suffix is unconditional,
including for a single-type reduction, so a multi-type per-type op cannot collide
with a single-type op sharing the same type-suffixed spelling.
Intrinsic-operator user reductions are named by their defining scope and ultimate
symbol, matching the defined-operator and named forms. Previously they used a
global name derived from the operator and element type, so two declare reductions
for the same operator and type in different scopes (two modules, or two
procedures in one file) could collide onto one op and silently bind the wrong
combiner. Builtin intrinsic reductions keep their global names.
For separate compilation the imported directive carries bound names but no typed
expressions, because mod-file reading runs only ResolveNames. The materializer
therefore runs expression analysis over the directive before lowering. Creating
the op from an imported module directive during lowering follows the imported
declare-mapper precedent.
An operator-less declare reduction (a special function such as max or min, or an
intrinsic operator such as `+` on an intrinsic type) has an internal mangled name
that is not valid Fortran, and no re-exported operator to recover through. When
such a reduction is re-exported through a facade, emitting it as a `use, only`
item produced a module file that failed to re-parse. The module-file writer
instead re-exports the defining module with a plain `use`, because a mangled name
cannot appear in an only-list. Entities the facade renames or makes private keep
their own use, rename, or private items, so the plain `use` does not widen their
visibility. The reduction then arrives as one shared use-association owned by the
defining module, binding the user's combiner rather than a facade-owned duplicate
that would fall back to the intrinsic. A private reduction is not re-exported.
When a reduction identifier resolves to more than one distinct user-defined
reduction for the list item's type, the clause is rejected as ambiguous rather
than selecting a combiner silently by USE order. Distinctness is by canonical
identity, the defining module and reduction name, so one reduction reached
through several USE, rename, or facade paths collapses to one candidate while
reductions from different modules stay separate. One case is not distinguished.
A same-named module loaded at two versions (a stale hermetic embed versus a
rebuilt copy) collapses to one candidate and is still resolved by USE order,
matching the prior behavior.
Assisted-by: Claude Opus 4.8, GPT-5.5.
Commit: 693ded3ecc9c18178c7fc7fc1186d624edb5e62f
https://github.com/llvm/llvm-project/commit/693ded3ecc9c18178c7fc7fc1186d624edb5e62f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[LLVM] Fix not passing CMAKE_CROSSCOMPILING_EMULATOR for amdgpu (#209828)
Summary:
This only matches on amdgcn, just add amdgpu
Commit: 3a10c3aa3c2087ca4e6f0a18e182ced84a8a7fd0
https://github.com/llvm/llvm-project/commit/3a10c3aa3c2087ca4e6f0a18e182ced84a8a7fd0
Author: Rashmi Mudduluru <r_mudduluru at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/include/clang/Frontend/SSAFOptions.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysis/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
A clang/test/Analysis/Scalable/PointerFlow/system-header-opt-out.cpp
M clang/test/Analysis/Scalable/help.cpp
M clang/unittests/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowTest.cpp
Log Message:
-----------
[clang][SSAF] Optionally skip system-header contributors (#205446)
A new —ssaf-no-extract-from-system-headers switch that gates the
contributor finder so contributors located inside system headers are
dropped from the per-TU summary.
rdar://179151040
---------
Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
Commit: 5979f7c96f44d225219d3c637773455e51190ad2
https://github.com/llvm/llvm-project/commit/5979f7c96f44d225219d3c637773455e51190ad2
Author: Letu Ren <fantasquex at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/test/CIR/CodeGenBuiltins/builtins-elementwise.c
Log Message:
-----------
[CIR][NFC] Update stale elementwise handler (#207530)
A follow up of https://github.com/llvm/llvm-project/pull/204974
Clean up stale code of https://github.com/llvm/llvm-project/pull/169424
Add two missing CIR elementwise tests
Add three missing elementwise builtins as NYI
Assisted-by: Codex
Commit: b8ba3c2b72cb53268129bbecfeb4ba7ec5b8d831
https://github.com/llvm/llvm-project/commit/b8ba3c2b72cb53268129bbecfeb4ba7ec5b8d831
Author: Reinhard Stahn <rainij36 at proton.me>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
A mlir/include/mlir/Conversion/SCFToAffine/SCFToAffine.h
M mlir/lib/Conversion/CMakeLists.txt
A mlir/lib/Conversion/SCFToAffine/CMakeLists.txt
A mlir/lib/Conversion/SCFToAffine/SCFToAffine.cpp
A mlir/test/Conversion/SCFToAffine/scf-to-affine.mlir
Log Message:
-----------
[mlir][SCFToAffine] Raise scf.for to affine.for (#200851)
Add a pass `-raise-scf-to-affine` that rewrites `scf.for` into
`affine.for` when the bounds and step are valid affine quantities. It
handles constant and dynamic steps, and integer-typed loops (by a
lossless cast of the bounds to `index`).
This is a first step; raising further scf ops to affine will follow.
Assisted-by: Claude Code (Anthropic)
Co-authored-by: Ming Yan <nexming7 at gmail.com>
Co-authored-by: Julian Farnsteiner <jcf96 at proton.me>
Commit: ea612545644d1e3f238ac4cd053758f569f9bf3b
https://github.com/llvm/llvm-project/commit/ea612545644d1e3f238ac4cd053758f569f9bf3b
Author: Karthika Devi C <kartc at qti.qualcomm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M polly/lib/CodeGen/BlockGenerators.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
A polly/test/CodeGen/issue205732.ll
Log Message:
-----------
[Polly] Fix codegen assertions to account for DefinedBehaviorContext (#209188)
DeLICM may produce new read access relations whose domain is restricted
to the DefinedBehaviorContext (e.g., only valid when a parameter ensures
no UB). The validation in setNewAccessRelation already accounts for
this, but the debug assertions in createNewAccesses and
generateScalarLoads did not, causing false assertion failures during
code generation.
Intersect the checked domains with getBestKnownDefinedBehaviorContext()
to match the contract that DeLICM relies on.
Fixes #205732
Commit: 378629b2200b092fa33e6171e7c749c95ff92e9c
https://github.com/llvm/llvm-project/commit/378629b2200b092fa33e6171e7c749c95ff92e9c
Author: anoopkg6 <anoop.kumar6 at ibm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
Log Message:
-----------
[flang] Derive target-specific data layout from triple in TargetRewrite (#209649)
When target-rewrite runs without an explicit llvm.data_layout attribute,
it falls back to hardcoded generic default in MLIR (kDefaultDataLayout)
which specifies f128 ABI alignment as 16 bytes. This is incorrect for
targets where f128 ABI alignment differs from its size, such as SystemZ
which requires 8 bytes per the ELF ABI.
The target triple is available in the target-rewrite pass. Fix by
deriving the data layout from the target triple using
triple.computeDataLayout() before falling back to the generic default,
ensuring target-specific alignments are correctly reflected in
dlti.dl_spec.
@uweigand @dominik-steenken
---------
Co-authored-by: anoop.kumar6 at ibm.com <anoopk at b35lp63.lnxne.boe>
Commit: 09a947e3d02cbd8a7afd273bddbcf9fe489bfe9c
https://github.com/llvm/llvm-project/commit/09a947e3d02cbd8a7afd273bddbcf9fe489bfe9c
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/test/API/driver/longpath/TestLongPathDriver.py
M lldb/test/API/functionalities/longpath/TestLongPath.py
M lldb/test/API/tools/lldb-dap/longpath/TestDAP_launch_longPath.py
M lldb/test/Shell/helper/toolchain.py
Log Message:
-----------
[lldb][Windows] Use extended path prefix for rmtree (#209409)
The test suite previously only warned when a test build directory or
artifact path exceeded Windows' `MAX_PATH (260)` limit, and
`shutil.rmtree` could fail to clean up such directories. This replaces
the warnings with actual long-path support.
This is a recurring problem in Swiftlang.
Commit: c4c4f207590a1569b5c30ffe2f204f5d0d535a68
https://github.com/llvm/llvm-project/commit/c4c4f207590a1569b5c30ffe2f204f5d0d535a68
Author: Schrodinger ZHU Yifan <yfzhu at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libc/src/__support/freelist.cpp
Log Message:
-----------
[libc][baremetal][NFC] cache away redundant freelist memory access during push and pop (#208282)
By explicitly caching Node *next = node->next; and Node *prev =
node->prev; at function entry:
#### Before (Original):
```llvm
13: ; preds = %6
%14 = load ptr, ptr %1, align 8 ; Load node->prev
%15 = getelementptr inbounds nuw i8, ptr %14, i64 8
store ptr %8, ptr %15, align 8 ; Store next to prev->next
%16 = load ptr, ptr %7, align 8 ; <--- REDUNDANT LOAD of node->next
store ptr %14, ptr %16, align 8 ; Store prev to next->prev
%17 = icmp eq ptr %3, %1
br i1 %17, label %18, label %20
18: ; preds = %13, %10
%19 = phi ptr [ null, %10 ], [ %16, %13 ]
store ptr %19, ptr %0, align 8
```
#### After (Manual GVN in remove ):
```llvm
13: ; preds = %6
%14 = load ptr, ptr %1, align 8 ; Load node->prev
%15 = getelementptr inbounds nuw i8, ptr %14, i64 8
store ptr %8, ptr %15, align 8 ; Store next to prev->next
store ptr %14, ptr %8, align 8 ; <--- REUSES CACHED %8 DIRECTLY
%16 = icmp eq ptr %3, %1
br i1 %16, label %17, label %19
17: ; preds = %13, %10
%18 = phi ptr [ null, %10 ], [ %8, %13 ] ; <--- REUSES CACHED %8 IN PHI NODE
store ptr %18, ptr %0, align 8
```
### 2. Compiler Optimization Remarks & LTO Impact
1. GVN Diagnostics:
• Before: freelist.cpp:41:11: remark: load of type ptr not eliminated
[-Rpass-missed=gvn]
• After: Clean (0 missed GVN remarks).
2. LTO (Link-Time Optimization) & Code Size:
Eliminates 1 memory read ( MOV64rm ) and 1 memory store ( MOV64mr ) at
every inlined call site in malloc / free.
Assisted-by: Gemini based automation tool (human-in-the-loop)
Commit: 27329918bf4c9430104449b9a5c0354f138417db
https://github.com/llvm/llvm-project/commit/27329918bf4c9430104449b9a5c0354f138417db
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
Log Message:
-----------
[AMDGPU] Limit unclaused VMEM w/a to specific targets (#209843)
Fixes: LCOMPILER-2448
Commit: be1b1a77732ce65d8de5f8316f0ce65e2be818ba
https://github.com/llvm/llvm-project/commit/be1b1a77732ce65d8de5f8316f0ce65e2be818ba
Author: Brandon Correa <bwancor at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/LineEditor/LineEditor.cpp
Log Message:
-----------
Turn signal handling on in LineEditor (#203616)
This PR was created to address
https://github.com/jank-lang/jank/issues/801.
Without signal handling, `CLRL+C` / `CTRL+Z` leaves the terminal in an
awkward state, breaking other command line tasks and forcing the user to
open a new/clean terminal window.
cc: @jeaye
### Edit
#### AI
Per the contribution policies and review practices, AI was used to
locate the root cause of the issue I was seeing. From there, I
personally wrote the code and manually tested the build to verify that
the change fixed the problem I was seeing.
#### Testing
Since there were no pre-existing unit tests for this module, no
additional unit tests were added for this PR. I validated the existing
build/tests locally and validated the change propagated through
manually.
Commit: 889b2d651a530952339e4992a2b5a891c7dd0af0
https://github.com/llvm/llvm-project/commit/889b2d651a530952339e4992a2b5a891c7dd0af0
Author: Dan Brown <61992655+danbrown-amd at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/HLSLControlFlowHint.hlsl
M clang/test/AST/HLSL/matrix-alias.hlsl
M clang/test/AST/HLSL/matrix-constructors.hlsl
M clang/test/AST/HLSL/matrix-elementexpr-tree-transform.hlsl
M clang/test/AST/HLSL/matrix-general-initializer.hlsl
M clang/test/AST/HLSL/matrix-member-access-scalar.hlsl
M clang/test/AST/HLSL/matrix-member-access-swizzle.hlsl
M clang/test/AST/HLSL/resources-in-structs-errors.hlsl
M clang/test/AST/HLSL/resources-in-structs.hlsl
M clang/test/AST/HLSL/vector-alias.hlsl
M clang/test/AST/HLSL/vector-constructors.hlsl
M clang/test/AST/HLSL/vk.spec-constant.usage.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/frem_modulo.hlsl
M clang/test/CodeGenHLSL/builtins/AllMemoryBarrier.hlsl
M clang/test/CodeGenHLSL/builtins/AllMemoryBarrierWithGroupSync.hlsl
M clang/test/CodeGenHLSL/builtins/DeviceMemoryBarrier.hlsl
M clang/test/CodeGenHLSL/builtins/DeviceMemoryBarrierWithGroupSync.hlsl
M clang/test/CodeGenHLSL/builtins/GroupMemoryBarrier.hlsl
M clang/test/CodeGenHLSL/builtins/GroupMemoryBarrierWithGroupSync.hlsl
M clang/test/CodeGenHLSL/builtins/InterlockedAdd.hlsl
M clang/test/CodeGenHLSL/builtins/InterlockedOr.hlsl
M clang/test/CodeGenHLSL/builtins/QuadReadAcrossDiagonal.hlsl
M clang/test/CodeGenHLSL/builtins/QuadReadAcrossX.hlsl
M clang/test/CodeGenHLSL/builtins/QuadReadAcrossY.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveAllEqual.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveAllTrue.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveAnyTrue.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBallot.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBitAnd.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBitXor.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveCountBits.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveMax.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveMin.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveProduct.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveSum.hlsl
M clang/test/CodeGenHLSL/builtins/WavePrefixCountBits.hlsl
M clang/test/CodeGenHLSL/builtins/WavePrefixProduct.hlsl
M clang/test/CodeGenHLSL/builtins/WavePrefixSum.hlsl
M clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
M clang/test/CodeGenHLSL/builtins/acos-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/acos.hlsl
M clang/test/CodeGenHLSL/builtins/all.hlsl
M clang/test/CodeGenHLSL/builtins/any.hlsl
M clang/test/CodeGenHLSL/builtins/asdouble.hlsl
M clang/test/CodeGenHLSL/builtins/asin-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/asin.hlsl
M clang/test/CodeGenHLSL/builtins/atan-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan.hlsl
M clang/test/CodeGenHLSL/builtins/atan2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan2-overloads_mat.hlsl
M clang/test/CodeGenHLSL/builtins/atan2.hlsl
M clang/test/CodeGenHLSL/builtins/atan2_mat.hlsl
M clang/test/CodeGenHLSL/builtins/clamp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/clamp.hlsl
M clang/test/CodeGenHLSL/builtins/clip.hlsl
M clang/test/CodeGenHLSL/builtins/cosh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/cosh.hlsl
M clang/test/CodeGenHLSL/builtins/cross.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-coarse-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-coarse.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-fine-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-fine.hlsl
M clang/test/CodeGenHLSL/builtins/ddx.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-coarse-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-coarse.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-fine-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-fine.hlsl
M clang/test/CodeGenHLSL/builtins/ddy.hlsl
M clang/test/CodeGenHLSL/builtins/degrees-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/degrees.hlsl
M clang/test/CodeGenHLSL/builtins/distance.hlsl
M clang/test/CodeGenHLSL/builtins/dot.hlsl
M clang/test/CodeGenHLSL/builtins/dot2add.hlsl
M clang/test/CodeGenHLSL/builtins/f16tof32-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f16tof32.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16.hlsl
M clang/test/CodeGenHLSL/builtins/faceforward.hlsl
M clang/test/CodeGenHLSL/builtins/firstbithigh.hlsl
M clang/test/CodeGenHLSL/builtins/firstbitlow.hlsl
M clang/test/CodeGenHLSL/builtins/fma.hlsl
M clang/test/CodeGenHLSL/builtins/fmod.hlsl
M clang/test/CodeGenHLSL/builtins/frac-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/frac.hlsl
M clang/test/CodeGenHLSL/builtins/isinf-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/isinf.hlsl
M clang/test/CodeGenHLSL/builtins/isnan.hlsl
M clang/test/CodeGenHLSL/builtins/length.hlsl
M clang/test/CodeGenHLSL/builtins/lerp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/lerp.hlsl
M clang/test/CodeGenHLSL/builtins/mad.hlsl
M clang/test/CodeGenHLSL/builtins/normalize-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/normalize.hlsl
M clang/test/CodeGenHLSL/builtins/radians-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/radians.hlsl
M clang/test/CodeGenHLSL/builtins/rcp.hlsl
M clang/test/CodeGenHLSL/builtins/reflect.hlsl
M clang/test/CodeGenHLSL/builtins/refract.hlsl
M clang/test/CodeGenHLSL/builtins/rsqrt-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/rsqrt.hlsl
M clang/test/CodeGenHLSL/builtins/sign.hlsl
M clang/test/CodeGenHLSL/builtins/sinh.hlsl
M clang/test/CodeGenHLSL/builtins/smoothstep.hlsl
M clang/test/CodeGenHLSL/builtins/step-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/step.hlsl
M clang/test/CodeGenHLSL/builtins/tan-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/tan.hlsl
M clang/test/CodeGenHLSL/builtins/tanh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/tanh.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-methods-ps.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Mips.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_geps.hlsl
M clang/test/CodeGenHLSL/semantics/semantic.explicit-mix-builtin.vs.hlsl
M clang/test/Driver/dxc_hlsl-rootsig-ver.hlsl
M clang/test/ParserHLSL/access_specifiers.hlsl
M clang/test/ParserHLSL/hlsl_contained_type_attr.hlsl
M clang/test/ParserHLSL/hlsl_contained_type_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_is_array_attr.hlsl
M clang/test/ParserHLSL/hlsl_is_array_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_is_rov_attr.hlsl
M clang/test/ParserHLSL/hlsl_is_rov_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_raw_buffer_attr.hlsl
M clang/test/ParserHLSL/hlsl_raw_buffer_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_resource_class_attr.hlsl
M clang/test/ParserHLSL/hlsl_resource_class_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_resource_dimension_attr.hlsl
M clang/test/ParserHLSL/hlsl_resource_dimension_attr_error.hlsl
M clang/test/ParserHLSL/semantic_parsing.hlsl
M clang/test/ParserHLSL/semantic_parsing_define.hlsl
M clang/test/SemaHLSL/Availability/attr-deprecated.hlsl
M clang/test/SemaHLSL/BuiltIns/binary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/fma-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/matrix-constructors-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/ternary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/unary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/vec-scalar-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/vector-constructors-errors.hlsl
M clang/test/SemaHLSL/Language/InitIncompleteArrays.hlsl
M clang/test/SemaHLSL/Language/InitLists.hlsl
M clang/test/SemaHLSL/Language/NoVirtual.hlsl
M clang/test/SemaHLSL/Language/OutputParameters.hlsl
M clang/test/SemaHLSL/Language/TemplateOutArg.hlsl
M clang/test/SemaHLSL/Resources/ConstantBuffers.hlsl
M clang/test/SemaHLSL/Semantics/semantic.explicit-mix-builtin-vs.hlsl
M clang/test/SemaHLSL/Semantics/semantic.explicit-mix-location-2.hlsl
M clang/test/SemaHLSL/Semantics/semantic.explicit-mix-location.hlsl
M clang/test/SemaHLSL/Semantics/valid_entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/vertexid.vs.hlsl
M clang/test/SemaHLSL/Types/short-errors.hlsl
M clang/test/SemaHLSL/entry_shader.hlsl
M clang/test/SemaHLSL/num_threads.hlsl
M clang/test/SemaHLSL/prohibit_reference.hlsl
M clang/test/SemaHLSL/vk.spec-constant.error.hlsl
Log Message:
-----------
[HLSL] Adds diagnostics for missing/ambiguous shader entry function. (#184892)
Addresses #119260.
Commit: 2dac2abaff714c099880d1d41066d2609563242e
https://github.com/llvm/llvm-project/commit/2dac2abaff714c099880d1d41066d2609563242e
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel][mlir] Port b8ba3c2b72cb53268129bbecfeb4ba7ec5b8d831 (#209854)
Add SCFToAffine target + deps
Commit: 0256ff92c9e1033270a73ba83d0f34865ef63202
https://github.com/llvm/llvm-project/commit/0256ff92c9e1033270a73ba83d0f34865ef63202
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/lit.cfg.py
Log Message:
-----------
[clang][test][AIX] Set OBJECT_MODE=any for all clang test (#209531)
This patch sets OBJECT_MODE=any to have tools able to handle 32-bit or
64-bit objects.
Commit: b74c800578a06bba7b3bacc690cbe493759836a2
https://github.com/llvm/llvm-project/commit/b74c800578a06bba7b3bacc690cbe493759836a2
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
Log Message:
-----------
[compiler-rt][tsan] Fix -Wunused-template in tsan_interface_atomic.cpp (NFC) (#209621)
Commit: 4e1a6091623a4d3b28132b6b4940a264511f5d0e
https://github.com/llvm/llvm-project/commit/4e1a6091623a4d3b28132b6b4940a264511f5d0e
Author: Steven Wu <stevenwu at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Sema/ExternalSemaSource.h
M clang/include/clang/Sema/MultiplexExternalSemaSource.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Serialization/ASTReader.h
M clang/lib/Sema/MultiplexExternalSemaSource.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/PCH/unused-local-typedef-determinism.cpp
A clang/test/SemaCXX/warn-unused-local-typedef-deterministic-order.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h
Log Message:
-----------
[Sema][Serialization] Emit unused local typedefs in a deterministic order (#209639)
Sema::UnusedLocalTypedefNameCandidates is populated while iterating a
Scope's
DeclsInScope, which is a SmallPtrSet whose iteration order depends on
pointer
values and is therefore not stable across runs. The candidates are
serialized
into the AST file -- both to assign declaration IDs and to write the
UNUSED_LOCAL_TYPEDEF_NAME_CANDIDATES record -- and are also used to emit
the
deferred -Wunused-local-typedef warnings, so neither the emitted PCH/AST
file
nor the diagnostics were reproducible. With deterministic compilation
caching
this surfaces as a "cache poisoned" error, because two builds of the
same PCH
produce different bytes.
Sort the candidates by source location at the point they are consumed,
via
Sema::getSortedUnusedLocalTypedefNameCandidates(), so that both the
diagnostics
and the serialized declarations are deterministic.
Commit: 26194d4623650fd3f9b58cda34b318197613e702
https://github.com/llvm/llvm-project/commit/26194d4623650fd3f9b58cda34b318197613e702
Author: Zachary Yedidia <zyedidia at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/docs/LFI.rst
M llvm/include/llvm/MC/MCLFIRewriter.h
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.h
M llvm/test/MC/AArch64/LFI/guard-elim.s
M llvm/test/MC/AArch64/LFI/mem-lr.s
A llvm/test/MC/AArch64/LFI/pac-errors.s
A llvm/test/MC/AArch64/LFI/pac.s
M llvm/test/MC/AArch64/LFI/return.s
Log Message:
-----------
[LFI][AArch64] Add PAC support for LFI (#207915)
This patch adds support for PAC instructions that sign `x30` by deferring
the LFI mask until the next control-flow instruction or label, allowing
an authentication instruction to run before the mask, which overwrites
the PAC signature bits in the top bits of the pointer. This relies on
FEAT_FPAC to provide a security benefit, which requires authentication
failure to cause a trap, rather than expecting the branch on an invalid
pointer to cause the trap.
Commit: 725f644a31627c08f6cec25a7eb2396ad690d08e
https://github.com/llvm/llvm-project/commit/725f644a31627c08f6cec25a7eb2396ad690d08e
Author: Björn Schäpers <bjoern at hazardy.de>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Improve requires clause parsing (#207542)
We did not consider dependent templates and thus ended the parsing after
template and forcing a line break there. The tests was formatted as:
template <typename T> struct S {
template <typename Foo>
requires T::template
Has<Foo> void func(Foo);
};
Commit: 105261293d6763055cecf7e37aced21de94eaefc
https://github.com/llvm/llvm-project/commit/105261293d6763055cecf7e37aced21de94eaefc
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/X86/fmaddsub-combine.ll
M llvm/test/CodeGen/X86/fmsubadd-combine.ll
Log Message:
-----------
[X86] fmaddsub-combine.ll + fmsubadd-combine.ll - cleanup 512-bit buildvector tests (#209850)
Followup to #207436 - the full buildvector and partial buildvector tests
are covered by PhaseOrdering/X86/fmaddsub.ll which outputs the (still
poor) vectorized shuffle patterns
Ensure the current middle-end IR is tested by the backend, even though
its still not optimal (and divergent between SSE and AVX targets) - I've
kept the buildvector backend patterns for now (and moved the buildvector
fmsubadd patterns to fmsubadd-combine.ll for consistency).
Next step will be to investigate why the middle-end IR result isn't
optimal.
Minor cleanup for #144489
Commit: f41f334bff98866aefa33f09ae67b61532afa4a5
https://github.com/llvm/llvm-project/commit/f41f334bff98866aefa33f09ae67b61532afa4a5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/Analysis/CostModel/AMDGPU/sin.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-log.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-uniform-waterfall.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-uniform-intrinsic-combine.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-uniform-temporal-divergence.ll
M llvm/test/CodeGen/AMDGPU/atomic-optimizer-promote-i8.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimization_split_dt_update.ll
M llvm/test/CodeGen/AMDGPU/disable-preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/do-not-unify-divergent-exit-nodes-with-musttail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.2dmsaa.ll
M llvm/test/CodeGen/AMDGPU/loop-vector-sink.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-barriers.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-cluster-barrier.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-split-barriers.ll
M llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll
M llvm/test/CodeGen/AMDGPU/printf_builtin.ll
M llvm/test/CodeGen/AMDGPU/printf_nobuiltin.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-budget-exhausted.ll
M llvm/test/CodeGen/AMDGPU/vni8-live-reg-opt.ll
M llvm/test/Transforms/AggressiveInstCombine/AMDGPU/fold-consecutive-loads.ll
M llvm/test/Transforms/AggressiveInstCombine/AMDGPU/fold-loads-multiple-uses.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i64-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i64-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-mmra.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-private-gas.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-flat-noalias-addrspace.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-fp-vector.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-integer-ops-0-to-add-0.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/phinode-address-infer.ll
M llvm/test/Transforms/InstCombine/AMDGPU/bitcast-fold-lane-ops.ll
M llvm/test/Transforms/InstCombine/AMDGPU/fmed3.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wave.shuffle.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wavefrontsize.ll
M llvm/test/Transforms/InstCombine/AMDGPU/mbcnt.ll
M llvm/test/Transforms/InstCombine/AMDGPU/rcp-contract-rsq.ll
M llvm/test/Transforms/InstCombine/AMDGPU/simplify-demanded-vector-elts-lane-intrinsics.ll
M llvm/test/Transforms/InstCombine/AMDGPU/trivially-uniform.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/load-i1-misaligned.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/buffer-fat-pointer.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/exp2-vectorize.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/external-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/extract-ordering.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/inst-count-heuristic.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/vectorize-i8.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/zext-duplicate-shift.ll
M llvm/test/Transforms/SandboxVectorizer/AMDGPU/basic.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/amdgpu-large-lds-offset.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/rebuild-trunc.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reunite-exts-source-types.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reunite-exts.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/combine-scalar-selects.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-i8.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/shuffles-of-length-changing-shuffles.ll
Log Message:
-----------
AMDGPU: Migrate tests with regenerated checks to amdgpu subarch triple (54) (#209780)
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
autogenerated tests where the folded triple changes output relative to
the previous default subtarget (e.g. cost-model BASE lines, scheduling).
CHECK lines were regenerated with the update_*_test_checks.py scripts.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 27836a16cd229d25413e23d7d14ebe2678385121
https://github.com/llvm/llvm-project/commit/27836a16cd229d25413e23d7d14ebe2678385121
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
M llvm/test/CodeGen/AMDGPU/debug-value.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-addressing-mode-loops.ll
Log Message:
-----------
AMDGPU: Migrate uniform target-cpu attribute tests to subarch triple (55) (#209815)
Commit: 96a722a0ace661626d071166635728def97f6820
https://github.com/llvm/llvm-project/commit/96a722a0ace661626d071166635728def97f6820
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-flat-scratch-init-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-intrinsic-missing-nocallback.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-nocallback-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-trap-leaf.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
M llvm/test/CodeGen/AMDGPU/attributor-wwm.ll
M llvm/test/CodeGen/AMDGPU/issue120256-annotate-constexpr-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
M llvm/test/CodeGen/AMDGPU/propagate-amdgpu-cluster-dims.ll
Log Message:
-----------
AMDGPU: Fold -mcpu into subarch triple for attributor tests (56) (#209816)
Commit: 90a2e5010fa88627cd21bd0311833c786be8a213
https://github.com/llvm/llvm-project/commit/90a2e5010fa88627cd21bd0311833c786be8a213
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll
Log Message:
-----------
[msan] Handle AVX512 mask.compress (#209654)
mask.compress selects elements from the first two operands according to
the mask; thus, we can propagate the shadow by applying the intrinsic to
the input shadows (with the mask unchanged i.e., trailingVerbatimArgs ==
1), using the forceIntegerIntrinsic option that was added in
https://github.com/llvm/llvm-project/pull/207053
Commit: d48f3ca0dc9027fd892336f7b4f046a6c5887c02
https://github.com/llvm/llvm-project/commit/d48f3ca0dc9027fd892336f7b4f046a6c5887c02
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll
M llvm/test/CodeGen/AMDGPU/call-encoding.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/inline-calls.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-sgmask.ll
M llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll
M llvm/test/CodeGen/AMDGPU/madmk-madak-encoding-size.ll
M llvm/test/CodeGen/AMDGPU/mesa_regression.ll
M llvm/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-shufflevector.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
M llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir
M llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
Log Message:
-----------
AMDGPU: Migrate more tests to using subarch triple commands (57) (#209817)
Mostly mechanical updates with some light cleanups manually
applied.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: c40401dd8d28e88519433531c041b0b7e5ada8a9
https://github.com/llvm/llvm-project/commit/c40401dd8d28e88519433531c041b0b7e5ada8a9
Author: Amy Kwan <amy.kwan1 at ibm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Object/GOFFObjectFile.cpp
Log Message:
-----------
[Object][GOFF] Recognize RLD and LEN records (#207118)
This patch adds explicit cases for RT_RLD and RT_LEN records when
parsing GOFF objects. These record types are not handled yet, but
recognizing them allows us to diagnose them and avoids teating them as
unexpected records.
Commit: 9d09c774832bc99cde76ecb4847bb01680da533d
https://github.com/llvm/llvm-project/commit/9d09c774832bc99cde76ecb4847bb01680da533d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Make VPBlockTy enum protected (NFC) (#209863)
VPBlockTy is an implementation detail, that is only needed in sub-types.
Make protected.
Commit: 0b18869a684febeb4144cd0213cef3163b8cb37e
https://github.com/llvm/llvm-project/commit/0b18869a684febeb4144cd0213cef3163b8cb37e
Author: Sirraide <aeternalmail at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/bindings/python/tests/cindex/test_diagnostics.py
M clang/include/clang/Basic/Diagnostic.td
M clang/include/clang/Basic/DiagnosticIDs.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Basic/DiagnosticIDs.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/SemaBase.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaType.cpp
Log Message:
-----------
[Clang] [Diagnostic] Extend DiagCompat() to C language modes (#209241)
This expands the compatibility warnings infrastructure added in #132348
to support C mode as well. Implementing this was actually fairly
straight-forward because we are only ever in C _or_ C++ mode, i.e.
during a single compilation we either emit only C compatibility warnings
or only C++ compatibility warnings. This means we can simply reuse the
existing code and just check for different LangOpts depending on whether
we're in C or C++ mode.
Concretely, this means that instead of e.g.
```
def ext_c2y_alignof_incomplete_array : Extension<
"'alignof' on an incomplete array type is a C2y extension">,
InGroup<C2y>;
def warn_c2y_compat_alignof_incomplete_array : Warning<
"'alignof' on an incomplete array type is incompatible with C standards "
"before C2y">, InGroup<CPre2yCompat>, DefaultIgnore;
```
you can now simply write
```
defm alignof_incomplete_array : C2yCompat<"'alignof' on an incomplete array type is">;
```
And when emitting the warning(s), code such as
```
Diag(OpLoc, getLangOpts().C2y
? diag::warn_c2y_compat_alignof_incomplete_array
: diag::ext_c2y_alignof_incomplete_array);
```
can now be replaced with
```
DiagCompat(OpLoc, diag_compat::alignof_incomplete_array);
```
I've also migrated the C compatibility warnings in
DiagnosticSemaKinds.td to use the new system to make sure that
everything is working properly.
Commit: 0f494fc6576600f79bbcdb5314fbed6c13da7395
https://github.com/llvm/llvm-project/commit/0f494fc6576600f79bbcdb5314fbed6c13da7395
Author: Vy Nguyen <1762963+oontvoo at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
M clang/test/CodeGen/attr-nomerge.cpp
A clang/test/CodeGen/builtin-trap.c
M clang/test/CodeGen/pr53127.cpp
M clang/test/CodeGenCXX/microsoft-abi-byval-vararg.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
M clang/test/CodeGenCXX/trap-fnattr.cpp
M clang/test/CodeGenCXX/vararg-non-pod.cpp
M clang/test/DebugInfo/CXX/verbose-trap.cpp
M clang/test/Headers/gpuintrin.c
M clang/test/OpenMP/spirv_target_codegen_noexceptions.cpp
M compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
Log Message:
-----------
[codegen]Ensure __builtin_trap() has an unreachable (#197789)
```
void test2() {
__builtin_trap();
}
```
Previously, this would generate this:
```
; Function Attrs: mustprogress noinline nounwind optnone uwtable
define dso_local void @test2()() #2 !dbg !14 {
call void @llvm.trap(), !dbg !15
ret void, !dbg !16
}
```
Now we'll have `unreachable` after the trap
```
; Function Attrs: noinline nounwind optnone uwtable
define dso_local void @test2() #0 {
call void @llvm.trap()
unreachable
}
```
Commit: 23ead65310da314ae04a1c30137f279beaac1a4f
https://github.com/llvm/llvm-project/commit/23ead65310da314ae04a1c30137f279beaac1a4f
Author: Patrik Dokoupil <61749375+pdokoupil at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc
A compiler-rt/test/msan/Linux/syscalls_setgroups.cpp
Log Message:
-----------
[compiler-rt][sanitizer_common] Fix setgroups syscall pre-hook to check its input (#209207)
# About
`PRE_SYSCALL(setgroups)`/`setgroups16` called `POST_WRITE` on their
`grouplist` argument, but grouplist is a read-only input the kernel
never writes. Under MSan, `POST_WRITE` maps to `__msan_unpoison`, so
annotating a raw setgroups(2) via the documented
`__sanitizer_syscall_pre_setgroups` hook silently marked an
uninitialized group list as initialized -- before the syscall even ran,
and even on failure -- masking a real use-of-uninitialized-value bug.
Under TSan it recorded a write range where a read belongs.
Use PRE_READ, matching every other input-only argument in this file
(e.g. sched_setparam). Add an MSan regression test.
Commit: 09599503b1314a0394e57adbd6279d9a220bfdb8
https://github.com/llvm/llvm-project/commit/09599503b1314a0394e57adbd6279d9a220bfdb8
Author: Arda Serdar Pektezol <arda at pektezol.dev>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
A llvm/test/Transforms/LowerTypeTests/icall-branch-funnel-invalid-operand.ll
Log Message:
-----------
[LowerTypeTests] Avoid null dereference on invalid branch funnel operand (#204951)
On the linked issue, a null dereference happens when looping over`
ArrayRef<GlobalTypeMember *> Globals` at
`LowerTypeTestsModule::buildBitSetsFromDisjointSet()`. This stems from
the external globals in the IR which don't enter GlobalTypeMembers.
Following that, operator[] over the DenseMap returns null and it
propagates to the looped over GlobalTypeMember.
Prevent the null dereference via `.find()` and reporting fatal usage
error if it is not present. Add a negative regression test.
Additionally, the LangRef for the `@llvm.icall.branch.funnel` intrinsic
is missing (see #133635). It would also be nice to have a Verifier entry
for this intrinsic, and get rid of most report_fatal_error() in this
file since it's deprecated.
Fixes #191985
---------
Co-authored-by: Vitaly Buka <vitalybuka at google.com>
Commit: ce586b57f4a8e32d47df58dc1b11730f07ffc834
https://github.com/llvm/llvm-project/commit/ce586b57f4a8e32d47df58dc1b11730f07ffc834
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512dq-intrinsics.ll
Log Message:
-----------
[msan] Handle AVX512 fpclass (floating-point classification) for packed double/float (#209652)
Each bit of the classifier constant specifies whether a particular
classifier is enabled. If Classifiers == 0 (no classifiers are enabled),
the output is trivially known to be zero, thus the output is fully
initialized.
Otherwise, each bit of the output is the bitwise OR of one or more
classifications; we approximate each bit of the output shadow based on
whether the corresponding input element is fully initialized (without
which the classification is potentially unknown). This is only
approximate, because some classifications do not rely on all the bits of
the input element.
This patch only handles packed double/single-precision floating-point.
Handling the scalar equivalents is more complicated because those
intrinsics encode a mask.
Commit: 835ae525713e27aa98c46469792cee980669c6ca
https://github.com/llvm/llvm-project/commit/835ae525713e27aa98c46469792cee980669c6ca
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M compiler-rt/lib/asan/asan_interceptors.cpp
Log Message:
-----------
[compiler-rt] Fix asan_interceptors.cpp build warning -Wunused-template (#209750)
mmap_interceptor/munmap_interceptor template functions are instantiated
in sanitizer_common_interceptors.inc only under `#if
SANITIZER_INTERCEPT_MMAP`. Fix `unused function template
'mmap_interceptor'` warning on Windows, which is error under -Werror.
Commit: 7021b428656d283626e9ab3c1a81795c1f6c7086
https://github.com/llvm/llvm-project/commit/7021b428656d283626e9ab3c1a81795c1f6c7086
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/induction-nowrap-from-scev-not-ir.ll
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-wrapping.ll
Log Message:
-----------
[ConstraintElim] Try to get induction step/start/flags from IR (NFC-ish) (#209284)
Handle the common integer inductions where the increment is plain add
PN, C by looking at IR instead of querying SCEV. There's effectively no
re-use between SCEV expression created in ConstraintElimination, and
handling simple cases in IR can avoid unnecessary, expensive SCEV
queries.
Should be NFC-ish. We miss trivial folding of the start value (see
regressed test), but that should not happen in end-to-end pipeline.
Improves compile-time for some workloads, ClamAV, mafft:
https://llvm-compile-time-tracker.com/compare.php?from=b8ba3c2b72cb53268129bbecfeb4ba7ec5b8d831&to=2bede223d3ec3ed6e2e9654b635258c50e4e90df&stat=instructions%3Au
I am working on follow-up changes that will handle more cases, where
avoiding unnecessary queries will be more important.
PR: https://github.com/llvm/llvm-project/pull/209284
Commit: 85204d0bce5b24fba24baa0b440b051b6d040f4c
https://github.com/llvm/llvm-project/commit/85204d0bce5b24fba24baa0b440b051b6d040f4c
Author: Paul Kirth <paulkirth at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
Log Message:
-----------
[libcxx] Mark test unsupported in clang-24 (#209794)
After the version bump, we started seeing this test fail. For now mark
it unsupported in newer LLVM versions, until the underlying issue can be
addressed. More details can be found in #209787.
Commit: 5c0dfced1adc55429e32b1db08570abd3a219d85
https://github.com/llvm/llvm-project/commit/5c0dfced1adc55429e32b1db08570abd3a219d85
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/AST/ByteCode/builtin-object-size.cpp
Log Message:
-----------
[clang][bytecode] Fix tail padding with __builtin_object_size (#209771)
This fixes the new libcxx/atomics/builtin_clear_padding.pass.cpp
Commit: 50f2b9443d23eba757c3c0f42eef71e0f9721b15
https://github.com/llvm/llvm-project/commit/50f2b9443d23eba757c3c0f42eef71e0f9721b15
Author: David Green <david.green at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-bf16.ll
R llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-fp-trunc-bf16.ll
Log Message:
-----------
[AArch64] Lower fixed width bf16 fpround (#209411)
Similar to #209194, this was previously hitting an error with an illegal
FP_ROUND_MERGE_PASSTHRU. This time we lower the fptrunc to a scalable
fptrunc and let it legalize naturally. On SVE systems a f64->bf16
fptrunc will fail to legalize, but lowers successfully with sve2 with
fcvtn. A store(fptrunc) -> truncstore combine was disabled too as it
fails with bf16.
Commit: ebd969054197c4767b0f47db0370ed26ac04c990
https://github.com/llvm/llvm-project/commit/ebd969054197c4767b0f47db0370ed26ac04c990
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Log Message:
-----------
[msan][NFCI] Add maybe_unused annotation for #209652 (#209878)
Fix compile error for non-assertion builds
(https://lab.llvm.org/buildbot/#/builders/228/builds/4987) after #209652
Commit: 03e3a6273adc16450c814a68444c1ca9e9768ce3
https://github.com/llvm/llvm-project/commit/03e3a6273adc16450c814a68444c1ca9e9768ce3
Author: Augusto Noronha <anoronha at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp
Log Message:
-----------
[lldb] Skip the prologue before reading `this` when stepping into std::function (#209629)
Commit 40152b8 broke CPPLanguageRuntime::GetStepThroughTrampolinePlan by
changing operator() from a multi-line function to a single line
function.
This used to work by accident, because the fallback step-in plan first
advanced past the prologue and the trampoline detection was re-invoked
there with a valid `this`. Once operator() became a one-line inline
definition that intermediate step no longer happened.
Run past the prologue when stopped at the function entry and let the
step-through machinery re-invoke the plan, so the thread plan has a
valid `this` to read from.
Commit: 77e9b8cc155911b5a1378b20cd5e98784ab8a365
https://github.com/llvm/llvm-project/commit/77e9b8cc155911b5a1378b20cd5e98784ab8a365
Author: Vijay Kandiah <vkandiah at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Lower/CUDA/cuda-implicit-managed-alloc.cuf
Log Message:
-----------
[flang][cuda] Skip implicit managed/unified attribution for COMMON objects (#209855)
Objects in Fortran `COMMON` blocks may not carry `ATTRIBUTES(MANAGED)`
or `ATTRIBUTES(UNIFIED)`. The implicit attribution added in
[#209292](https://github.com/llvm/llvm-project/pull/209292) did not
account for this, causing a spurious semantic error when a pointer in a
`COMMON` block was implicitly attributed. This change adds a
`!object->commonBlock()` guard to `SetImplicitCUDADataAttr` so that
COMMON members are left unattributed.
Commit: 2cffd1922d06ec79f3c602c4434280450f50f8ba
https://github.com/llvm/llvm-project/commit/2cffd1922d06ec79f3c602c4434280450f50f8ba
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[NFC][PowerPC] Delete redundant ISD::TRUNCATE from setTargetDAGCombine (#200902)
there is
```
setTargetDAGCombine({ISD::TRUNCATE, ISD::VECTOR_SHUFFLE});
if (Subtarget.useCRBits()) {
setTargetDAGCombine({ISD::TRUNCATE, ISD::SETCC, ISD::SELECT_CC}); }
```
we do not need to set the (ISD::TRUNCATE again when
Subtarget.useCRBits()
Commit: cf293b069a6a1938bcef9271b04b6abc9e3292f8
https://github.com/llvm/llvm-project/commit/cf293b069a6a1938bcef9271b04b6abc9e3292f8
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M .github/new-prs-labeler.yml
A clang/docs/AMDGPUSupport.md
R clang/docs/AMDGPUSupport.rst
A clang/docs/APINotes.md
R clang/docs/APINotes.rst
A clang/docs/AllocToken.md
R clang/docs/AllocToken.rst
A clang/docs/BoundsSafety.md
R clang/docs/BoundsSafety.rst
A clang/docs/BoundsSafetyAdoptionGuide.md
R clang/docs/BoundsSafetyAdoptionGuide.rst
A clang/docs/BoundsSafetyImplPlans.md
R clang/docs/BoundsSafetyImplPlans.rst
A clang/docs/CIR/index.md
R clang/docs/CIR/index.rst
A clang/docs/CXXTypeAwareAllocators.md
R clang/docs/CXXTypeAwareAllocators.rst
A clang/docs/ClangPlugins.md
R clang/docs/ClangPlugins.rst
A clang/docs/CommandGuide/index.md
R clang/docs/CommandGuide/index.rst
A clang/docs/ControlFlowIntegrity.md
R clang/docs/ControlFlowIntegrity.rst
A clang/docs/DebuggingCoroutines.md
R clang/docs/DebuggingCoroutines.rst
A clang/docs/ExternalClangExamples.md
R clang/docs/ExternalClangExamples.rst
A clang/docs/FAQ.md
R clang/docs/FAQ.rst
A clang/docs/IntroductionToTheClangAST.md
R clang/docs/IntroductionToTheClangAST.rst
A clang/docs/LibClang.md
R clang/docs/LibClang.rst
A clang/docs/LibFormat.md
R clang/docs/LibFormat.rst
A clang/docs/LibTooling.md
R clang/docs/LibTooling.rst
A clang/docs/RISCVSupport.md
R clang/docs/RISCVSupport.rst
A clang/docs/Tooling.md
R clang/docs/Tooling.rst
Log Message:
-----------
[docs] Rename selected Clang docs to Markdown (#209281)
Tracking issue: https://github.com/llvm/llvm-project/issues/201242
Migration guide docs:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
RFC:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840
This is the initial straight rename commit. It will probably break the
docs build, but it has to be a separate PR for blame preservation
purposes.
Commit: 1514df333358c221db20f841ecdbcc217409e89f
https://github.com/llvm/llvm-project/commit/1514df333358c221db20f841ecdbcc217409e89f
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/AMDGPUSupport.md
M clang/docs/APINotes.md
M clang/docs/AllocToken.md
M clang/docs/BoundsSafety.md
M clang/docs/BoundsSafetyAdoptionGuide.md
M clang/docs/BoundsSafetyImplPlans.md
M clang/docs/CIR/index.md
M clang/docs/CXXTypeAwareAllocators.md
M clang/docs/ClangPlugins.md
M clang/docs/CommandGuide/index.md
M clang/docs/ControlFlowIntegrity.md
M clang/docs/DebuggingCoroutines.md
M clang/docs/ExternalClangExamples.md
M clang/docs/FAQ.md
M clang/docs/IntroductionToTheClangAST.md
M clang/docs/LibClang.md
M clang/docs/LibFormat.md
M clang/docs/LibTooling.md
M clang/docs/RISCVSupport.md
M clang/docs/Tooling.md
Log Message:
-----------
[docs] Rewrite selected Clang docs to Markdown (#209283)
Tracking issue: https://github.com/llvm/llvm-project/issues/201242
Migration guide docs:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
RFC:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840
This was prepared with rst2myst plus LLM-assisted cleanup. I paged
through all the generated HTML looking for migration artifacts, and all
of the differences I could find appear to be formatting error
corrections.
I noticed that there is a large block of literal rst text in APINotes.md, but I will defer that for later cleanup.
Commit: b1cf1e5719c4673fc464083a8e93a585497a9f8b
https://github.com/llvm/llvm-project/commit/b1cf1e5719c4673fc464083a8e93a585497a9f8b
Author: Mircea Trofin <mtrofin at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/FixedMetadataKinds.def
M llvm/lib/IR/Globals.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
M llvm/lib/Transforms/Utils/AssignGUID.cpp
M llvm/lib/Transforms/Utils/CloneModule.cpp
Log Message:
-----------
[NFC] rename `MD_unique_id` to `MD_guid` for consistency (#209880)
Commit: 195991885bce0b232b4f5aab16ff87d34473f464
https://github.com/llvm/llvm-project/commit/195991885bce0b232b4f5aab16ff87d34473f464
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/CIR/CodeGenBuiltins/builtin-call.cpp
M clang/test/CIR/CodeGenHLSL/matrix-element-expr-load.hlsl
Log Message:
-----------
[CIR] Fix a pair of CIR Build failures: (#209896)
HLSL added a bunch of diagnostics for entry functions that messed with
the matrix test, see here:
https://github.com/llvm/llvm-project/pull/184892/
The solution is to just mark the test as a library triple.
Builtin-trap stopped translating in classic codegen, so the call after
it is now missing (and there is an unreachable after it),w hich actually
better matches our behavior see:
https://github.com/llvm/llvm-project/pull/197789
This patch fixes both tests.
Commit: bfcea5d5f5c36097963c338b3609aee93242a573
https://github.com/llvm/llvm-project/commit/bfcea5d5f5c36097963c338b3609aee93242a573
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
Log Message:
-----------
[VPlan] Add VPlan print test for expanding SCEV with AddRec (NFC). (#209886)
Commit: 1ffd509c4b109fd894f67b2f1d8159d281e0f13a
https://github.com/llvm/llvm-project/commit/1ffd509c4b109fd894f67b2f1d8159d281e0f13a
Author: Nikhil Kalra <nikhil.kalra at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.h
Log Message:
-----------
[TableGen][GISel] Fix Matcher Creation for C++23 libc++ (#209783)
libc++ in C++23 mode evaluates make_unique eagerly, which requires
InstructionMatcher to be defined at the constexpr call to make_unique.
Currently, it's defined later in the file.
This patch moves the call to make_unique to the C++ file so that
InstructionMatcher is fully defined at time of instantiation.
Commit: c63bfe581cad89409e711a4c62fbf3de6cd42b40
https://github.com/llvm/llvm-project/commit/c63bfe581cad89409e711a4c62fbf3de6cd42b40
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Support/Fortran-features.cpp
M flang/test/Lower/CUDA/cuda-init.cuf
M flang/tools/bbc/bbc.cpp
Log Message:
-----------
[flang][cuda] Decouple CUFInit from CUDA language features (#209846)
In some cases, we do not want to emit the CUFInit function in the main.
Add a specific language feature for it so we can decouple it.
Commit: e5c19b0ebc54206348273fc2f7cf67cb195908ed
https://github.com/llvm/llvm-project/commit/e5c19b0ebc54206348273fc2f7cf67cb195908ed
Author: nitro <nitro123 at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M bolt/lib/Core/BinaryContext.cpp
A bolt/test/X86/jump-table-failed-reanalysis.s
Log Message:
-----------
[BOLT] Skip function instead of aborting on jump table analysis failure (#206742)
`analyzeJumpTable()` runs twice on a candidate jump table: once from
`analyzeMemoryAt` while the referencing function is being disassembled,
and
again from `populateJumpTables()` after disassembly. The second run is
stricter,
because the check that an entry points at an instruction
(`getInstructionAtOffset`) only fires once the target function reaches
the
`Disassembled` state. A table can therefore be accepted the first time
and
rejected the second -- for instance when an entry lands at an address
with no
instruction (a symbol whose declared size is larger than its
disassembled
extent). `populateJumpTables()` reached `llvm_unreachable("jump table
heuristic
failure")` and aborted in that case.
Handle it the way BOLT already handles indirect branches it can't
analyze: drop
the table and skip the owning function(s) via `addFragmentsToSkip()`.
The
`JumpTable` is deliberately left in the maps so it is still freed by
`~BinaryContext` (an earlier attempt at this, 52cd00ca, was reverted in
468d4f6d
because it erased the table without deallocating it).
New test `jump-table-failed-reanalysis.s` builds such a table; before
this change
BOLT aborts, after it the function is skipped and the rest of the binary
is
processed normally.
Commit: f7c4b05863cd9ffdcedf95c03480f1e6198c9bb7
https://github.com/llvm/llvm-project/commit/f7c4b05863cd9ffdcedf95c03480f1e6198c9bb7
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang-rt/lib/runtime/cudadevice.f90
Log Message:
-----------
[flang][cuda] Add PURE to time intrinsic so it can be used in DO CONCURRENT (#209901)
Commit: 1b5eb9b48dddd17b88f61f4718db357fbd2f8ed4
https://github.com/llvm/llvm-project/commit/1b5eb9b48dddd17b88f61f4718db357fbd2f8ed4
Author: Schrodinger ZHU Yifan <yfzhu at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/src/__support/freelist_heap.h
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/baremetal/CMakeLists.txt
A libc/src/stdlib/baremetal/malloc_usable_size.cpp
A libc/src/stdlib/malloc_usable_size.h
M libc/test/src/__support/freelist_heap_test.cpp
Log Message:
-----------
[libc][baremetal] expose `malloc_usable_size` from freelist heap (#208337)
Expose the `malloc_usable_size` API by reconstruct the `BlockRef` from a
pointer to the head of user payload. The operation is cheap as we only
do a query to the block header to obtain the metadata.
Assisted-by: Gemini based automation tools (human-in-the-loop)
Commit: 18d2b47a0d3b6bb5d55260e69bf51c47de8e0dc6
https://github.com/llvm/llvm-project/commit/18d2b47a0d3b6bb5d55260e69bf51c47de8e0dc6
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/MC/MCObjectFileInfo.h
Log Message:
-----------
[NFC] Remove unused MCObjectFileInfo methods (#209906)
Commit: ba2be3f8add2e63266686cb1bcd40c9fab07de7b
https://github.com/llvm/llvm-project/commit/ba2be3f8add2e63266686cb1bcd40c9fab07de7b
Author: Kewen Meng <Kewen.Meng at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M offload/test/lit.cfg
Log Message:
-----------
[Offload][AMDGPU] Make compiler-rt libs visible (#209849)
Fixed the failure in offload test after
https://github.com/llvm/llvm-project/pull/209765
Commit: b6059b6ce21886c3f8644355ae9017cf3ba04aad
https://github.com/llvm/llvm-project/commit/b6059b6ce21886c3f8644355ae9017cf3ba04aad
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/lib/CodeGen/TargetSchedule.cpp
M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/X86/X86CmovConversion.cpp
A llvm/test/CodeGen/RISCV/sched-model-load-latency.ll
A llvm/test/CodeGen/RISCV/sched-model-mispredict-penalty.ll
Log Message:
-----------
[MCSched] Allow tuning LoadLatency/MispredictPenalty (#203139)
This means an existing scheduling model can be tweaked at runtime to
support an unknown processor rather than adding an entirely new model.
This is done with TargetSubtargetInfo so that specific targets can
override the relevant callbacks and the mechanism can eventually work
with LTO.
Commit: 670841415d3d5d1f85eb5859096880678967fd4e
https://github.com/llvm/llvm-project/commit/670841415d3d5d1f85eb5859096880678967fd4e
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_breakpointLocations.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setBreakpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setExceptionBreakpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setFunctionBreakpoints.py
Log Message:
-----------
[lldb-dap] Migrate lldb-dap tests in `lldb-dap/breakpoint` (#208166)
migrate breakpointLocations, logpoints, setBreakpoints
exceptionBreakpoints and functionBreakpoints test
Commit: f9bda52e57a759d20224cd581f73f61ee3220e74
https://github.com/llvm/llvm-project/commit/f9bda52e57a759d20224cd581f73f61ee3220e74
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/bmi.ll
M llvm/test/CodeGen/X86/bmi2.ll
Log Message:
-----------
[X86][APX] Add EVEX BMI opcodes to isDefConvertible (#209699)
To remove redundant test instructions.
Fixes: #207912
Assisted-by: Claude Sonnet 4.6
Commit: ff1a4d3c197c6210941caaa639edfa722fc8896c
https://github.com/llvm/llvm-project/commit/ff1a4d3c197c6210941caaa639edfa722fc8896c
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
A llvm/test/TableGen/CodeEmitterBaseEncodingPool.td
M llvm/test/TableGen/HwModeEncodeAPInt.td
M llvm/utils/TableGen/CodeEmitterGen.cpp
Log Message:
-----------
[TableGen] Pool duplicate code-emitter base encodings (#202619)
Pool duplicate multiword instruction base encodings across the default
encoding table and all hardware-mode encoding tables as unique `APInt`
rows, then emit a pointer-free fixed-width `uint64_t` row table and one
smallest-width opcode-to-row index table per mode. Use the pooled
representation only when the combined values and indices are smaller
than the original tables.
On a Release build, the AMDGPU base-encoding payload shrinks by 440,888
bytes, `llvm-mc` and `llc` each shrink by 445,632 bytes, and the LLVM
driver shrinks by 429,120 bytes.
All 421 TableGen tests passed.
Work towards #202616
AI tool disclosure: Co-authored with OpenAI Codex.
Commit: 2ac025b406e9b62ca3ae0af42a3d9d5dc649c234
https://github.com/llvm/llvm-project/commit/2ac025b406e9b62ca3ae0af42a3d9d5dc649c234
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenFunction.cpp
Log Message:
-----------
Make Multiversion Function Resolvers set CurFn (#209918)
Commit #197789 manages to try to reference CurFn while generating a
trap, which some of the multiversion resolvers do. This patch makes sure
we set it to the resolver so we are inserting stuff into the right
places.
This somewhat shockingly causes no tests to fail, but it SHOULD stop the
UBSan failures.
Commit: f020acfd395d9094303e78c807bc168a46a783fa
https://github.com/llvm/llvm-project/commit/f020acfd395d9094303e78c807bc168a46a783fa
Author: Fei Peng <pengfei.02 at bytedance.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_platform.h
M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
Log Message:
-----------
[tsan] Add 47-bit VMA mapping for linux/aarch64 (#205949)
Add 47-bit VMA mapping to support TSan on the latest Android
emulator(16kb page size and 47 va bits).
Fixes https://github.com/llvm/llvm-project/issues/151931
Android kernel config:
https://android.googlesource.com/kernel/build/+/refs/heads/main-kernel-2026/kleaf/impl/defconfig/arm64_16k_defconfig#6
Commit: d4676e649ba86d7c389e1afe6d9ed4d8443e23ef
https://github.com/llvm/llvm-project/commit/d4676e649ba86d7c389e1afe6d9ed4d8443e23ef
Author: Henrik G. Olsson <hnrklssn at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/AST/ByteCode/builtin-object-size.cpp
Log Message:
-----------
[clang][bytecode] long double on arm64 darwin is 8 bytes (NFC) (#209930)
This test was failing on arm64 darwin targets. Generalise the #if so
that the win32 branch is also taken by arm64 darwin.
rdar://182340494
Commit: 047f12725a95425195f96b246300e782808322a3
https://github.com/llvm/llvm-project/commit/047f12725a95425195f96b246300e782808322a3
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/io/TestDAP_io.py
M lldb/test/API/tools/lldb-dap/launch/io/DAP_launch_io.py
M lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_integratedTerminal.py
M lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_internalConsole.py
M lldb/test/API/tools/lldb-dap/launch/io/main.cpp
Log Message:
-----------
[lldb-dap] Migrate DAP io tests. (#209538)
the launch_io* tests now allow testing args, input, and environment
together.
Previously, these test configurations were mutually exclusive. They are
now combined, removing the need to create a separate test for each input
source.
Migrated Tests:
- TestDAP_io.py
- TestDAP_launch_io_integratedTerminal.py
- TestDAP_launch_io_internalConsole.py
Commit: cc79c8cdc4e7f0a8a968e1d8c5b91b14ce1e183a
https://github.com/llvm/llvm-project/commit/cc79c8cdc4e7f0a8a968e1d8c5b91b14ce1e183a
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMIR.cpp
A clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zihintntl.c
Log Message:
-----------
[CIR][RISCV] Support Zihintntl builtins (#205468)
Include __builtin_riscv_ntl_load and __builtin_riscv_ntl_store.
Commit: 071b86797f62e827bf18e83667b0d1875a5ee446
https://github.com/llvm/llvm-project/commit/071b86797f62e827bf18e83667b0d1875a5ee446
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
A llvm/test/CodeGen/Mips/fake-use.ll
Log Message:
-----------
[Mips] Did not put fake_use into delay slot (#201537)
When compiling with -fextend-variable-liveness, the compiler generates FAKE_USE instructions that are not handled by the Mips assembly printer. This causes a fatal error: "Unsupported instruction : <MCInst 44 >" when using clang with -target mipsel-gnu-linux -Og.
The issue occurs because MipsDelaySlotFiller attempts to process FAKE_USE instructions (which are meta instructions) when searching for instructions to fill delay slots, eventually leading to the assembly printer trying to emit an unsupported instruction.
This patch fixes the crash by treating meta instructions (including FAKE_USE) the same way as debug instructions in the delay slot filler's searchRange function. Meta instructions should be skipped during delay slot filling.
Specifically, the fix:
1.Moves the terminateSearch check before debug/meta instruction checks to ensure proper search termination.
2.Adds isMetaInstruction() check alongside existing isDebugInstr() and isJumpTableDebugInfo() checks.
Fix #198835.
Commit: 1f9891c05cd1faa3c1d27af444180fe2cb5f7786
https://github.com/llvm/llvm-project/commit/1f9891c05cd1faa3c1d27af444180fe2cb5f7786
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/MC/MCSchedule.h
Log Message:
-----------
[MCSchedule][NFC] Use constexpr for static constants (#209934)
Hopefully fixes a compilation error seen in llvm/llvm-project#203139.
Commit: 31b3a0ab54e21a5d38fa83bdcce3e3aa07e2cb1e
https://github.com/llvm/llvm-project/commit/31b3a0ab54e21a5d38fa83bdcce3e3aa07e2cb1e
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Target/Cpp/common-cpp.mlir
Log Message:
-----------
[mlir][emitc] Add increment and decrement ops (#208648)
Commit: 503c44707051a2c1b804013e40c26714030dfc18
https://github.com/llvm/llvm-project/commit/503c44707051a2c1b804013e40c26714030dfc18
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
Log Message:
-----------
[CycleInfo] Drop GraphTraits and df_iterator. NFC (#209847)
depth_first uses SmallPtrSet visited-set, which is pure overhead on a
tree. Replace them with explicit child-stack walks and delete the unused
GraphTraits specializations to prevent misuse.
Commit: fc77e9da83e7b850edc336d1d6c4e4c50ff8ac43
https://github.com/llvm/llvm-project/commit/fc77e9da83e7b850edc336d1d6c4e4c50ff8ac43
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/ObjectYAML/COFFYAML.h
M llvm/include/llvm/ObjectYAML/yaml2obj.h
M llvm/lib/ObjectYAML/COFFEmitter.cpp
M llvm/lib/ObjectYAML/yaml2obj.cpp
A llvm/test/tools/yaml2obj/COFF/output-limit.yaml
M llvm/tools/yaml2obj/yaml2obj.cpp
Log Message:
-----------
[yaml2obj] Apply output size limit to COFF (#209695)
Route the yaml2obj max-size setting through the COFF emitter and
buffer COFF output with ContiguousBlobAccumulator. This rejects
oversized YAML descriptions consistently with ELF.
Commit: bedbc79101106c143bfee9049ba74317dfa8b417
https://github.com/llvm/llvm-project/commit/bedbc79101106c143bfee9049ba74317dfa8b417
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Inline EVL pattern into single match call in optimizeLatchExitInductionUser. NFC (#209953)
This was waiting on m_HeaderMask to be introduced at the time it was
added.
Commit: 48607d29847349a617d4416c7be820032881a5a0
https://github.com/llvm/llvm-project/commit/48607d29847349a617d4416c7be820032881a5a0
Author: sohail <sohailraj.satapathy at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/stdfix.rst
M libc/include/stdfix.yaml
M libc/src/__support/fixed_point/CMakeLists.txt
M libc/src/__support/fixed_point/fx_bits.h
M libc/src/__support/fixed_point/fx_rep.h
M libc/src/stdfix/CMakeLists.txt
A libc/src/stdfix/divik.cpp
A libc/src/stdfix/divik.h
A libc/src/stdfix/divilk.cpp
A libc/src/stdfix/divilk.h
A libc/src/stdfix/divilr.cpp
A libc/src/stdfix/divilr.h
A libc/src/stdfix/divir.cpp
A libc/src/stdfix/divir.h
A libc/src/stdfix/diviuk.cpp
A libc/src/stdfix/diviuk.h
A libc/src/stdfix/diviulk.cpp
A libc/src/stdfix/diviulk.h
A libc/src/stdfix/diviulr.cpp
A libc/src/stdfix/diviulr.h
A libc/src/stdfix/diviur.cpp
A libc/src/stdfix/diviur.h
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/DiviFxTest.h
A libc/test/src/stdfix/divik_test.cpp
A libc/test/src/stdfix/divilk_test.cpp
A libc/test/src/stdfix/divilr_test.cpp
A libc/test/src/stdfix/divir_test.cpp
A libc/test/src/stdfix/diviuk_test.cpp
A libc/test/src/stdfix/diviulk_test.cpp
A libc/test/src/stdfix/diviulr_test.cpp
A libc/test/src/stdfix/diviur_test.cpp
Log Message:
-----------
[libc][stdfix] Implement divifx functions in LLVM libc (#206115)
Fixes #129124
Commit: 0216376fc192256a434d9eeb5c2782cdbdcdb1f6
https://github.com/llvm/llvm-project/commit/0216376fc192256a434d9eeb5c2782cdbdcdb1f6
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx11.cpp
Log Message:
-----------
[clang][bytecode] Diagnose pointer subtractions of elements of different arrays (#209496)
Commit: 687fbfae778ac2953c35920fb042446ef967c239
https://github.com/llvm/llvm-project/commit/687fbfae778ac2953c35920fb042446ef967c239
Author: Alok Kumar Sharma <AlokKumar.Sharma at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/IPO/MergeFunctions.h
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
A llvm/test/Transforms/MergeFunc/merge-functions-branch-weights.ll
A llvm/test/Transforms/MergeFunc/merge-functions-reordered-blocks-branch-weights.ll
A llvm/test/Transforms/MergeFunc/merge-functions-select-weights.ll
A llvm/test/Transforms/MergeFunc/merge-functions-value-profile.ll
M llvm/unittests/Transforms/IPO/MergeFunctionsTest.cpp
Log Message:
-----------
[MergeFunctions] Preserve instruction-level profile metadata during merging (#208009)
Merge branch weights and value profile metadata when equivalent
functions are folded. Branch weights are relative, so we scale them
to absolute counts via BlockFrequencyInfo before combining. Value
profile counts are already absolute, so we just sum them directly.
Commit: 75403b0b186f492b57bcb64f4a4b1c7716b11d98
https://github.com/llvm/llvm-project/commit/75403b0b186f492b57bcb64f4a4b1c7716b11d98
Author: Kazu Hirata <kazu at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/Eytzinger.h
M llvm/unittests/ADT/EytzingerTest.cpp
Log Message:
-----------
[ADT] Introduce EytzingerTable (#209343)
This patch introduces EytzingerTable, an owning container that stores
elements in a complete binary search tree formatted in Eytzinger
(breadth-first) order.
EytzingerTable::create is templated on the input container's value type,
allowing heterogeneous table construction such as building an
EytzingerTable<support::ulittle64_t> directly from a vector of native
uint64_t keys.
RFC:
https://discourse.llvm.org/t/rfc-faster-sample-profile-loading/90957/7
Assisted-by: Antigravity
Commit: 6705f3d3d2e6e9a151505375ab567ec82c54a637
https://github.com/llvm/llvm-project/commit/6705f3d3d2e6e9a151505375ab567ec82c54a637
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
Log Message:
-----------
[SLP][Modularisation][NFC] Extract commutativity and ordering helpers into SLPUtils 2/3 (#209080)
Please refer to RFC:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
Move into SLPVectorizer/SLPUtils.{h,cpp} (namespace
llvm::slpvectorizer):
- UsesLimit (constant)
- isCommutative(Instruction *, Value *, bool)
- isCommutative(Instruction *) (overload)
- isCommutableOperand
- getNumberOfPotentiallyCommutativeOps
- getElementIndex
- inversePermutation
- reorderScalars
- shortBundleName (debug-only, #if !defined(NDEBUG))
- areAllOperandsNonInsts
- isUsedOutsideBlock
- doesNotNeedToBeScheduled
- doesNotNeedToSchedule
(Please note that the move is intended to be verbatim. I welcome
comments about latents issues/comment changes and any other simple
things but will take them in a separate patch.)
Assisted by Cursor.
Commit: 2b1a6e1857ccedb2f006721412177f4be45581b0
https://github.com/llvm/llvm-project/commit/2b1a6e1857ccedb2f006721412177f4be45581b0
Author: Pranav Kant <prka at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
Fix Bazel build for 48607d2 (#209960)
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=48607d29847349a617d4416c7be820032881a5a0
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: ed0ea836f6cc029b3c8ec9b2308f5e94038dac03
https://github.com/llvm/llvm-project/commit/ed0ea836f6cc029b3c8ec9b2308f5e94038dac03
Author: WMC <tnwilly at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm-mma-fp8.mlir
Log Message:
-----------
[NVGPU] Add FP8 (e4m3/e5m2) support to nvgpu.mma.sync (#207342)
This PR is stacked on #207307
## Description
Add FP8 E4M3/E5M2 support for `nvgpu.mma.sync`, building on the
NVVM-level
support in #207307. This adds NVGPU verification and lowering support,
registers
the supported `m16n8k16`/`m16n8k32` MMA variants, and adds coverage for
NVGPU
lowering and NVVM verification.
## Test
```sh
mlir-opt mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm-fp8.mlir \
-convert-nvgpu-to-nvvm -split-input-file
```
Co-authored with Claude Sonnet 5
---------
Signed-off-by: weimin023 <tnwilly at gmail.com>
Commit: 745b946cbbf30708044b4a2c4a7726d0c02ca0de
https://github.com/llvm/llvm-project/commit/745b946cbbf30708044b4a2c4a7726d0c02ca0de
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx11.cpp
Log Message:
-----------
Revert "[clang][bytecode] Diagnose pointer subtractions of elements of different arrays" (#209969)
Reverts llvm/llvm-project#209496
Breaks the new virtual-bases.cpp test
Commit: 89a4b2f880a7b852cb9b4ff20a1e38a6b3a037a5
https://github.com/llvm/llvm-project/commit/89a4b2f880a7b852cb9b4ff20a1e38a6b3a037a5
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libc/hdr/CMakeLists.txt
A libc/hdr/sys_select_macros.h
A libc/hdr/sys_wait_macros.h
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/fd_set.h
A libc/hdr/types/struct_rusage.h
A libc/hdr/types/struct_utsname.h
M libc/src/sys/select/linux/CMakeLists.txt
M libc/src/sys/select/linux/select.cpp
M libc/src/sys/select/select.h
M libc/src/sys/utsname/linux/CMakeLists.txt
M libc/src/sys/utsname/linux/uname.cpp
M libc/src/sys/utsname/uname.h
M libc/src/sys/wait/linux/CMakeLists.txt
M libc/src/sys/wait/wait4.h
M libc/src/sys/wait/wait4Impl.h
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/gethostname.cpp
Log Message:
-----------
[libc] Replace sys/select.h, sys/utsname.h and sys/wait.h includes with proxy headers (#209851)
I'm replacing system includes of <sys/select.h>, <sys/utsname.h>, and
<sys/wait.h> in non-test and non-proxy code with granular proxy headers.
- add proxy headers for sys/select.h and sys/wait.h macros as well as
fd_set, struct rusage, and struct utsname types
- switch select, uname, gethostname, and wait4 internal headers and
implementations to include the proxy headers instead of system headers
- update cmake dependencies for the affected entry points
Assisted by Gemini.
Commit: 5a530a22fae4aaa41da79779cd56db57f8de55f8
https://github.com/llvm/llvm-project/commit/5a530a22fae4aaa41da79779cd56db57f8de55f8
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libc/include/llvm-libc-macros/netinet-in-macros.h
M libc/test/include/netinet_in_test.cpp
Log Message:
-----------
[libc] Reimplement IN6_IS_ADDR_* macros using statement expressions (#209772)
This patch fixes three issues with the previous implementation:
- the macro argument was being evaluated more than once
- casting to other types (uint32_t in particular) was an aliasing
violation
- it was casting to non-const pointers, resulting in compiler errors in
cases where the user passes a const ptr.
A statement expression fixes the first issue by using a temporary
variable. The second issue is fixed by using the appropriate members of
struct in6_addr. The last issue is fixed by dropping the cast
completely. This requires the user to pass a correctly types pointer (as
POSIX requires). Implementations keep it for compatibility with old code
passing void * and similar, but a quick survey shows that most modern
code passes the correct types. If this turns out to be an issue, we can
easily add the cast (to a const type) back.
Implementation notes:
- IN6_IS_ADDR_MULTICAST doesn't use the statement expression because the
argument is evaluated only once
- I use private helper macros (__IN6_IS_ADDR_UNSPECIFIED and
__IN6_IS_ADDR_LOOPBACK) so IN6_IS_ADDR_V4COMPAT does not nest statement
expressions
- I considered using private entrypoints (like we do with cpuset macros)
instead of statement expressions, but decided against it because these
macros are simpler and would thus result in a higher
boilerplate-to-useful-code ratio (particularly given our restriction on
calling other entrypoints)
Assisted by Gemini.
Commit: 762941070b1824ba5dc0a6b6a9e8c9dc4b5911e8
https://github.com/llvm/llvm-project/commit/762941070b1824ba5dc0a6b6a9e8c9dc4b5911e8
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M orc-rt/lib/executor/StandaloneMachOUnwindInfoRegistrar.cpp
M orc-rt/lib/executor/Unix/NativeDylibAPIs.inc
M orc-rt/lib/executor/Unix/NativeMemoryAPIs.inc
M orc-rt/lib/executor/sps-ci/MemoryAccessSPSCI.cpp
M orc-rt/test/unit/AllocActionTest.cpp
M orc-rt/test/unit/CompilerTest.cpp
M orc-rt/test/unit/ErrorCAPITest.cpp
M orc-rt/test/unit/ErrorExceptionInteropTest.cpp
M orc-rt/test/unit/ErrorTest.cpp
M orc-rt/test/unit/LockedAccessTest.cpp
M orc-rt/test/unit/QueueingRunnerTest.cpp
M orc-rt/test/unit/RTTITest.cpp
M orc-rt/test/unit/SPSWrapperFunctionTest.cpp
M orc-rt/test/unit/ThreadPoolRunnerTest.cpp
M orc-rt/test/unit/WrapperFunctionBufferTest.cpp
Log Message:
-----------
[orc-rt] Close with "// namespace" consistently. NFC. (#209979)
Commit: ac067a7e1366f1a9fca74b2cb69d6b005c6b732e
https://github.com/llvm/llvm-project/commit/ac067a7e1366f1a9fca74b2cb69d6b005c6b732e
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-bf16.ll
Log Message:
-----------
[AMDGPU] Use v_pk_add_bf16 for scalar bf16 fadd on gfx1250/gfx13 (#209128)
Targets with packed bf16 instructions can do a scalar bf16 fadd with a
single `v_pk_add_bf16` operating on the low half, instead of promoting
to f32 and going through `v_fma_mix_f32_bf16 + v_cvt_pk_bf16_f32`.
Commit: 76ee189f61dfbe249159ed7e0e772b50b4eb7aeb
https://github.com/llvm/llvm-project/commit/76ee189f61dfbe249159ed7e0e772b50b4eb7aeb
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/IPO/MergeFunctions.h
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
R llvm/test/Transforms/MergeFunc/merge-functions-branch-weights.ll
R llvm/test/Transforms/MergeFunc/merge-functions-reordered-blocks-branch-weights.ll
R llvm/test/Transforms/MergeFunc/merge-functions-select-weights.ll
R llvm/test/Transforms/MergeFunc/merge-functions-value-profile.ll
M llvm/unittests/Transforms/IPO/MergeFunctionsTest.cpp
Log Message:
-----------
Revert "[MergeFunctions] Preserve instruction-level profile metadata during merging" (#209987)
Reverts llvm/llvm-project#208009
Causes unit test failures.
Commit: 4ffab8581b9f35ed3934762aa9b9baf0fd84084f
https://github.com/llvm/llvm-project/commit/4ffab8581b9f35ed3934762aa9b9baf0fd84084f
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
Log Message:
-----------
[Mips] Fix test after #201537 (#209993)
Commit: ab1c8f643667ce85ec11dcfbdadac13e06291ce2
https://github.com/llvm/llvm-project/commit/ab1c8f643667ce85ec11dcfbdadac13e06291ce2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/docs/HIPSupport.md
Log Message:
-----------
clang/HIP: Update documentation for class name (#209992)
Commit: f5dfaa6dc5e85b6fbd4eb9f7eadef3ee010894d8
https://github.com/llvm/llvm-project/commit/f5dfaa6dc5e85b6fbd4eb9f7eadef3ee010894d8
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/test/Transforms/InstCombine/mul.ll
Log Message:
-----------
[InstCombine] Teach takeLog2 log2(X + 1) IIF X[0,1] -> X (#209741)
proof: https://alive2.llvm.org/ce/z/B7WjCg
Commit: 29cf2fb0116d6e13f81913440a41f577d11de664
https://github.com/llvm/llvm-project/commit/29cf2fb0116d6e13f81913440a41f577d11de664
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/unittests/CodeGen/RematerializerTest.cpp
Log Message:
-----------
[CodeGen] Fine-grained LIS updates on remat and dead-def handling (#202673)
This replaces the rematerializer's manual bulk LIS update paradigm in
favor of an automated fine-grained one that
1. performs LIS updates as rematerializations happen and
2. handles the removal of dead-definitions properly (this replaces the
prior partial handling of live interval splitting).
The new approach should be less error-prone (clients do not have to
periodically update the LIS, which is now up-to-date at all times from
the client's perspective) and faster in general (live intervals aren't
fully re-created every time a def or use of a register changes).
Handling dead-definitions (through a `LiveRangeEditor`) adds some
complexity to the rematerializer since unrematerializable MIs can now
also be deleted. This is exposed to listeners through a new event.
Furthermore, rematerializable registers can now become "permanently
dead" if all their users were unrematerializable MIs that became dead as
a result of other rematerializations.
The combination of these two improvements makes handling live-interval
splitting unnecessary. Rematerializable registers have a single-def by
construction so cannot ever have multiple disconnected components. On
the other hand, if we remove dead definitions as they appear,
unrematerializable registers's live interval cannot become made up of
multiple disconnected components purely as a result of
rematerializations. It is the rematerializer's client responsibility to
ensure that the LIS is in a valid state before the rematerializer
analyses the function.
Commit: 4536b1c44ebb54780f04e1ec992547d70a2d9700
https://github.com/llvm/llvm-project/commit/4536b1c44ebb54780f04e1ec992547d70a2d9700
Author: Mateusz Chudyk <mateusz.chudyk at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/combine-fdiv-inlineasm-operand.mir
M llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
Log Message:
-----------
[GlobalISel] Fix crash in isConstantOrConstantSplatVectorFP for non-register operands
isConstantOrConstantSplatVectorFP unconditionally accessed operand 0 as
a register, which causes a crash when the instruction is INLINEASM
(whose operand 0 is the asm string, not a register def).
This can happen when matchRepeatedFPDivisor walks the use-def chain of a
G_FDIV operand and reaches an INLINEASM instruction that defines the
dividend.
Commit: 09f8509bec1fec4636c8e592dcd55a80f39f2667
https://github.com/llvm/llvm-project/commit/09f8509bec1fec4636c8e592dcd55a80f39f2667
Author: ilia-cher <30845429+ilia-cher at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/unittests/Target/AMDGPU/GCNRegPressureTest.cpp
Log Message:
-----------
[AMDGPU] Fix speculative register pressure queries (#208574)
There are two issues with the way we currently speculate register
pressure:
1. GCNDownwardRPTracker::advance(with UseInternalIterator=false), which
is called by the scheduler in schedNode, resets LastTrackedMI, so the
tracker (bumpDownwardPressure) doesn't know where the last scheduled
instruction is and falls back to the beginning of the basic block. As a
result, when we estimate RP impact for a given MI, we tend to find uses
that are often already scheduled and should be skipped.
2. When looking for the remaining uses between LastTrackedMI and the
candidate MI we should skip already scheduled instruction.
Commit: ca6fe413daa538440cf47d4734051e3be7293600
https://github.com/llvm/llvm-project/commit/ca6fe413daa538440cf47d4734051e3be7293600
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
Log Message:
-----------
[LangRef] State that the memory model is an axiomatic one (#208710)
Currently, one could read large parts of the memory model without learning for
sure whether it is meant as an operational model that describes how individual
operations change some notion of state or if it is an axiomatic model (like the
C++ memory model) that lists constraints that a candidate execution must
satisfy to be allowed.
While the description of what a read returns sounds somewhat operational,
aspects like the definition of fence instructions, the monotonic modification
order, and the total order of sequentially consistent operations place it in
the realm of axiomatic models.
This is an attempt to make the nature of the model more explicit (and maybe a
place to discuss the nature of the model), as suggested by RalfJung in the
reviews for #204329.
Commit: aa199a3bc9d4ecdf87026d4db8dbb52bffa40605
https://github.com/llvm/llvm-project/commit/aa199a3bc9d4ecdf87026d4db8dbb52bffa40605
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
Log Message:
-----------
AMDGPU: Fix creating temporary TTI in AMDGPUCodeGenPrepare (#209976)
This should always be queried from the pass manager
Co-authored-by: Claude (Claude Opus 4.8) <noreply at anthropic.com>
Commit: 2bc2229f40028c66f6fe5956659570b55133035c
https://github.com/llvm/llvm-project/commit/2bc2229f40028c66f6fe5956659570b55133035c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/DebugInfo/AMDGPU/bitcast-store-combine-debugloc.ll
M llvm/test/DebugInfo/AMDGPU/cfi.ll
M llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll
M llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll
M llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll
M llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll
M llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-cfi-directives.s
M llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll
M llvm/test/DebugInfo/AMDGPU/print-reg-name.s
M llvm/test/DebugInfo/AMDGPU/variable-locations.ll
M llvm/test/DebugInfo/AMDGPU/wqm-wwm-debug-loc.ll
Log Message:
-----------
AMDGPU: Migrate DebugInfo tests to new subarch triples (58) (#209818)
Mostly mechanical by script
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 0f6a60fd6a2f54e5af99bb5c7c85e794b2ff3841
https://github.com/llvm/llvm-project/commit/0f6a60fd6a2f54e5af99bb5c7c85e794b2ff3841
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/CodeGen/MIR/AMDGPU/cfi-pseudos.mir
M llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
M llvm/test/CodeGen/MIR/AMDGPU/dead-flag-on-use-operand-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/instr-mmra-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/instr-mmra.mir
M llvm/test/CodeGen/MIR/AMDGPU/killed-flag-on-def-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-min-num-agprs.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-expect-id.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-parse.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-undefine-matadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-cfi-unsigned-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-name-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-mfi.ll
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-stack-type-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/ptradd-flags.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu-errors.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_loadcnt_dscnt-errors.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_loadcnt_dscnt.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt-errors.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt_soft.mir
M llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtreg-uses-unallocatable-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-split.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
Log Message:
-----------
AMDGPU: Migrate MIR parser tests to new subarch triples (59) (#209819)
Mechanical migration by script.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 041149970208fd709524e3b19c6aff4b41b58813
https://github.com/llvm/llvm-project/commit/041149970208fd709524e3b19c6aff4b41b58813
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize-with-call.ll
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize.ll
M llvm/test/tools/llvm-split/AMDGPU/declarations.ll
M llvm/test/tools/llvm-split/AMDGPU/indirect-call-inline-asm-debug.ll
M llvm/test/tools/llvm-split/AMDGPU/indirect-call-inline-asm.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-cost-ranking.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-duplication.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-external.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-indirect-callee-md.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-indirect.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-overridable.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables-noexternal.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-load-balancing.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-no-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging-weak_odr.ll
M llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging.ll
M llvm/test/tools/llvm-split/AMDGPU/non-kernels-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/non-kernels-dependency-indirect.ll
M llvm/test/tools/llvm-split/AMDGPU/preserve-globals.ll
M llvm/test/tools/llvm-split/AMDGPU/recursive-search-2.ll
M llvm/test/tools/llvm-split/AMDGPU/recursive-search-8.ll
Log Message:
-----------
AMDGPU: Use amdgpu triples in llvm-split tests (60) (#209866)
Update by regex
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: dab4c918c2453cc5650563571c35c6949bf5c611
https://github.com/llvm/llvm-project/commit/dab4c918c2453cc5650563571c35c6949bf5c611
Author: roman1741941 <rdivacky at vlakno.cz>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/RegisterBankEmitter.cpp
Log Message:
-----------
[TableGen] Optimize register bank and info emission. (#208297)
Don't go via a BitVector just to a read a single value out of it.
Commit: 88acd428fd72f44312408c3fb6165992fb3b043a
https://github.com/llvm/llvm-project/commit/88acd428fd72f44312408c3fb6165992fb3b043a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/Analysis/KernelInfo/enable-kernel-info/amdgpu.test
M llvm/test/Analysis/KernelInfo/flat-addrspace/amdgpu.test
M llvm/test/Analysis/KernelInfo/launch-bounds/amdgpu.ll
M llvm/test/Analysis/KernelInfo/openmp/README.md
M llvm/test/Analysis/KernelInfo/openmp/amdgpu.ll
Log Message:
-----------
AMDGPU: Migrate KernelInfo tests to new subarch triples (61) (#209867)
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 36d2fb92bcac253e2e1bb20b7ea7b22033027691
https://github.com/llvm/llvm-project/commit/36d2fb92bcac253e2e1bb20b7ea7b22033027691
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
Log Message:
-----------
[AMDGPU] Reject sub-dword format buffer loads and stores (#209703)
An i8 `buffer.{load,store}.format` has no corresponding hardware
instruction so diagnose it in SelectionDAG and fail legalization in
GlobalISel instead of emitting invalid format opcodes
Commit: 65d3601c44632bd0b5b90d559953cbd47442c0e2
https://github.com/llvm/llvm-project/commit/65d3601c44632bd0b5b90d559953cbd47442c0e2
Author: Jesse Huang <jesse.huang at sifive.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
A llvm/test/CodeGen/RISCV/short-forward-branch-opt-zibi.ll
Log Message:
-----------
[RISC-V] Make Short Forward Branches capable of matching Zibi instructions (#208637)
Add new SFB patterns to make `PseudoCCMOVGPR` capable of matching `beqi`
and `bnei`, so that it can be folded into `PseudoCC*` of `SFBALU_rr`
variants
Commit: 8a77787a526e31f48dd4d6f4cd9d68b982d8b772
https://github.com/llvm/llvm-project/commit/8a77787a526e31f48dd4d6f4cd9d68b982d8b772
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/bitcnt-load-with-cmov.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
Log Message:
-----------
Revert "[X86] Remove redundant `cmp` before `adc` after `lzcnt` or `tzcnt`" (#210006)
Reverts #208392 - while we investigate a miscompile due to CF/ZF mismatch
Commit: bf397be011e2cecce6ca0c1d0342eef217a06059
https://github.com/llvm/llvm-project/commit/bf397be011e2cecce6ca0c1d0342eef217a06059
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/include/llvm/IR/Instructions.h
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/test/Assembler/atomic.ll
A llvm/test/Assembler/invalid-load-store-atomic-elementwise.ll
A llvm/test/Bitcode/atomic-load-store-elementwise.ll
M llvm/test/Bitcode/compatibility.ll
M llvm/unittests/IR/VerifierTest.cpp
Log Message:
-----------
[IR] Add elementwise modifier to atomic loads (#204556)
Add an `elementwise` modifier to atomic loads to represent
per-element atomic semantics for fixed-vector loads.
Without the modifier, a vector atomic load remains a whole-value
atomic operation. With `elementwise`, the load behaves as if it were
expanded into one scalar atomic load per fixed-vector element, without
providing atomicity for the vector value as a whole.
Discussion:
https://discourse.llvm.org/t/rfc-add-elementwise-modifier-to-atomic-loads-and-stores/91100
Commit: 9c6a9f5fa37ffc21d4561301772bc600bd344d4c
https://github.com/llvm/llvm-project/commit/9c6a9f5fa37ffc21d4561301772bc600bd344d4c
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
Log Message:
-----------
[CodeGen][ARM64EC] Copy first four arguments to FP registers in vararg exit thunks (#209581)
ARM64EC vararg functions receive all types of the first four arguments
in x0-x3. Because x86_64 expects floating-point arguments in FP
registers, always copy x0-x3 to d0-d3 in the exit thunks, matching
MSVC's behavior.
Commit: c012610ab9924f465baea5e62397056ea9594567
https://github.com/llvm/llvm-project/commit/c012610ab9924f465baea5e62397056ea9594567
Author: Ben Dunbobbin <Ben.Dunbobbin at sony.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M cross-project-tests/CMakeLists.txt
A cross-project-tests/dtlto/remote-options.test
Log Message:
-----------
[DTLTO] Add remote compiler option forwarding coverage (#208589)
Add a cross-project DTLTO test that checks the existing LTO
configuration state serialized into the remote Clang command line. The
test uses the validate.py distributor to inspect the generated DTLTO
JSON.
Cover all the existing forwarded options.
Add paired negative checks for optional flags so the test also verifies
they are not emitted when the corresponding configuration state is not
set.
Commit: d94df008e71552fe5e07fa789bfa7f097cfdb0d9
https://github.com/llvm/llvm-project/commit/d94df008e71552fe5e07fa789bfa7f097cfdb0d9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/tools/llvm-reduce/mir/drop-ir-references.mir
M llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
M llvm/test/tools/llvm-reduce/mir/infer-triple.mir
M llvm/test/tools/llvm-reduce/mir/input-file-does-not-exist.mir
M llvm/test/tools/llvm-reduce/mir/instr-reduce-dead-def.mir
M llvm/test/tools/llvm-reduce/mir/multiple-functions.mir
M llvm/test/tools/llvm-reduce/mir/preserve-block-info.mir
M llvm/test/tools/llvm-reduce/mir/preserve-frame-info.mir
M llvm/test/tools/llvm-reduce/mir/preserve-func-info.mir
M llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir
M llvm/test/tools/llvm-reduce/mir/preserve-max-call-frame-size.mir
M llvm/test/tools/llvm-reduce/mir/preserve-mem-operands.mir
M llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
M llvm/test/tools/llvm-reduce/mir/reduce-instruction-flags.mir
M llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-defs.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-hints.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-masks.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-uses.mir
M llvm/test/tools/llvm-reduce/mir/remove-frame-destroy.mir
M llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
M llvm/test/tools/llvm-reduce/mir/subreg-def1.mir
M llvm/test/tools/llvm-reduce/mir/tracks-reg-liveness.mir
M llvm/test/tools/llvm-reduce/mir/undef-virt-reg.mir
Log Message:
-----------
AMDGPU: Convert llvm-reduce tests to new subarch triples (62) (#209868)
Pick arbitrary real subarch
Commit: fb2feebb64a6975f993791d86f00b085d6cd3bca
https://github.com/llvm/llvm-project/commit/fb2feebb64a6975f993791d86f00b085d6cd3bca
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction-cost.ll
Log Message:
-----------
[RISCV][VPlan] Cost vp.merges that are likely to be folded away as free (#209387)
A vp.merge is lowered to a PseudoVMERGE_VVM on RISC-V, and
RISCVVectorPeehole usually folds away PseudoVMERGE_VVMs when its true
operand is a binary op.
This accounts for this in the cost model and plumbs it through the loop
vectorizer. The following reduction loop was previously considered
unprofitable to vectorize, but after this change is now vectorized, and
folds away all its vp.merges:
void three_gathers(const long *a, const long *c, const long *d,
const long *b, long n, long *out) {
long s1 = 0, s2 = 0, s3 = 0;
for (long i = 0; i < n; i++) {
long j = b[i];
s1 += a[j];
s2 += c[j];
s3 += d[j];
}
out[0] = s1;
out[1] = s2;
out[2] = s3;
}
Some vp.merges have only phis for their operands which can't be folded
away, coming from FindLastIV reductions. So this extends and reuses the
VectorInstrContext hint to limit the discount when one of the operands
is a binary op.
Also see the commit message in 9e77f59005917e32f09136fa43018f471267f5bd
which mentions the vp.merge cost should be updated.
Commit: c1ba7d0aaad6baa898c6735f71a99791839a1847
https://github.com/llvm/llvm-project/commit/c1ba7d0aaad6baa898c6735f71a99791839a1847
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/ByteCode/virtual-bases.cpp
Log Message:
-----------
Reapply "[clang][bytecode] Diagnose pointer subtractions of elements … (#209998)
…of different arrays" (#209969)
This reverts commit 745b946cbbf30708044b4a2c4a7726d0c02ca0de.
Use only one `fold()` for the virtual base offset assertions.
The pointer subtraction _is_ invalid, but the current interpreter
doesn't diagnose it since the `LValueDesignator`s are invalid.
Commit: 2b8125c686614ffc5c5f8cde007cd6ddcf6649d8
https://github.com/llvm/llvm-project/commit/2b8125c686614ffc5c5f8cde007cd6ddcf6649d8
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/OpenCLExtensions.def
A clang/test/Misc/amdgcn.unsupported_core_3.1.cl
M clang/test/SemaOpenCL/extension-version.cl
Log Message:
-----------
[Clang][OpenCL] Promote a few extensions to OpenCL 3.1 core (#204330)
Following 6 OpenCL extensions are promoted to core features in 3.1:
https://github.com/KhronosGroup/OpenCL-Docs/commit/9fff1a87a975
- cl_khr_extended_bit_ops
- cl_khr_integer_dot_product
- cl_khr_subgroup_extended_types
- cl_khr_subgroup_rotate
- cl_khr_subgroup_shuffle
- cl_khr_subgroup_shuffle_relative
A target claiming OpenCL C 3.1 conformance without supporting one of
these features is now diagnosed.
Updated release notes for the change.
Assisted-by: Claude
Commit: adc0f685fe94e66e68698ac87a8595e878477a61
https://github.com/llvm/llvm-project/commit/adc0f685fe94e66e68698ac87a8595e878477a61
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-llvm-debuginfo-analyzer.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
M llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll
M llvm/test/CodeGen/AMDGPU/debug-independence-revertScheduling.ll
M llvm/test/CodeGen/AMDGPU/debug-independence-scheduleRegion.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-attributes.ll
M llvm/test/CodeGen/AMDGPU/issue176578.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-check-metadata.ll
M llvm/test/CodeGen/AMDGPU/pr155452.ll
M llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-phi.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/vgpr-count-compute.ll
M llvm/test/CodeGen/AMDGPU/vgpr-count-graphics-chain.ll
M llvm/test/CodeGen/AMDGPU/vgpr-count-graphics.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
Log Message:
-----------
AMDGPU: Convert tests to use subarch from triples in the file (#209869)
This set was using target triple in the source rather than command
line arguments.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 9277129afc6be0e4cf919bce1e0d2c56521af654
https://github.com/llvm/llvm-project/commit/9277129afc6be0e4cf919bce1e0d2c56521af654
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/convergent.mir
M llvm/test/CodeGen/AMDGPU/generic-targets-require-v6.ll
M llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll
Log Message:
-----------
AMDGPU: Use subarch in tests using generic arches (#209870)
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 65180a50117244b4758e03175bed2dc34fc74f91
https://github.com/llvm/llvm-project/commit/65180a50117244b4758e03175bed2dc34fc74f91
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
Log Message:
-----------
[VPlan] Relax address constraints during stride analysis (#209168)
VPlanTransforms::convertToStridedAccesses() only handled loads whose
address was a VPWidenGEPRecipe, missing pointer-induction loops where
the address is computed differently. Analyze the address VPValue
directly so these cases are also converted to strided loads.
Fixed #207171
Commit: 9b5ad6ee5dc5139f2a156350da64a84df8145fc6
https://github.com/llvm/llvm-project/commit/9b5ad6ee5dc5139f2a156350da64a84df8145fc6
Author: 311Volt <41923095+311Volt at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M offload/liboffload/API/Program.td
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.h
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.h
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/level_zero/include/L0Trace.h
M offload/plugins-nextgen/level_zero/src/L0Program.cpp
M offload/unittests/OffloadAPI/common/Environment.cpp
M offload/unittests/OffloadAPI/common/Environment.hpp
M offload/unittests/OffloadAPI/program/olCreateProgram.cpp
Log Message:
-----------
[offload] add translation of plugin-specific error codes to Offload API ECs (#207208)
liboffload plugins would not always exhaustively map the underlying
API's error values to ol_errc_t, resulting in unintended behavior - e.g.
olCreateProgram, given an invalid binary, would return OL_ERRC_UNKNOWN
instead of OL_ERRC_INVALID_BINARY.
This patch largely eliminates the most glaring cases of this by
assigning an ol_errc_t value to every error code of the underlying API
in every plugin. The proper granularity for this mapping is per-API
call, but that is a large rework that belongs in a separate patch.
Assisted-by: Claude
Commit: 83582cfcdb4973a337195c1f59d6a3468d135434
https://github.com/llvm/llvm-project/commit/83582cfcdb4973a337195c1f59d6a3468d135434
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/test/CodeGen/c11atomics.c
Log Message:
-----------
[clang][CodeGen] Do not use atomicrmw in compound assignments with FP conversions (#209114)
Per C11 6.5.16.2p1, when the left operand of operator `+=` has atomic
type, the right shall have arithmetic type. Do not try the `atomicrmw`
fast-path when FP conversion, arithmetic and truncation are required, as
a single atomic operation may not correctly capture the combined
semantics.
Fixes: https://github.com/llvm/llvm-project/issues/208997.
Commit: 59d7709ee9352df286bfb9b7a3b97c38deae5495
https://github.com/llvm/llvm-project/commit/59d7709ee9352df286bfb9b7a3b97c38deae5495
Author: Shikhar Jain <shikharj at qti.qualcomm.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M polly/lib/Transform/DeLICM.cpp
A polly/test/DeLICM/outofquota-greedycollapse.ll
Log Message:
-----------
Bound ISL operations during DeLICM scalar collapsing (#203073)
The IslMaxOperationsGuard in DeLICM previously covered only the zone
analysis performed in computeZone(). The subsequent greedyCollapse() ->
collapseScalarsToStore() path calls computeScalarReachingOverwrite(),
which performs an unbounded ISL lexmin().
Share a single[already present], dormant IslMaxOperationsGuard across
both regions and arm it narrowly around each operation intensive
computation via IslQuotaScope, so the same operations budget covers both
computeZone() and the scalar collapsing. When the quota is exceeded
during scalar collapsing, bail out cleanly: increment DeLICMOutOfQuota
and emit an "OutOfQuota" analysis remark.
Fixes: https://github.com/llvm/llvm-project/issues/202045
Commit: ad792fafbe64b3889ffac6e06bdd2a91ab8591bb
https://github.com/llvm/llvm-project/commit/ad792fafbe64b3889ffac6e06bdd2a91ab8591bb
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
Log Message:
-----------
[SLP][NFC] Address follow-up cleanups in SLPUtils (#210016)
Follow-up to #206881, addressing deferred review comments:
- Assert VL is non-empty in allSameType before consume_front.
- Use llvm::all_of instead of std::all_of in allSameOpcode.
- Rewrite isVectorLikeInstWithConstOps as a dyn_cast + opcode switch.
---------
Co-authored-by: Antonio Frighetto <me at antoniofrighetto.com>
Commit: 20a86a2fb7a793a59d7535ceb4d0f67c07b2f10e
https://github.com/llvm/llvm-project/commit/20a86a2fb7a793a59d7535ceb4d0f67c07b2f10e
Author: 311Volt <41923095+311Volt at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M offload/unittests/OffloadAPI/program/olCreateProgram.cpp
Log Message:
-----------
[offload] fix failure of olCreateProgramTest.TruncatedBinary (#210024)
https://github.com/llvm/llvm-project/pull/207208 caused a CI failure on
openmp-offload-amdgpu-clang-flang in the
olCreateProgramTest.TruncatedBinary test.
This PR removes this test case, as it's unclear whether guarding against
such cases is worth it.
Commit: 83eac376c5dfc4e730955f37a48f24850e0b5a52
https://github.com/llvm/llvm-project/commit/83eac376c5dfc4e730955f37a48f24850e0b5a52
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M flang/include/flang/Lower/PFTBuilder.h
M flang/lib/Lower/PFTBuilder.cpp
A flang/test/Lower/pre-fir-tree-multiway-branch.f90
M flang/test/Lower/pre-fir-tree02.f90
Log Message:
-----------
[flang][PFT] record every target of multiway branches (#210012)
The Evaluation node stored branch targets in a single `Evaluation *`
(`controlSuccessor`). `markBranchTarget` therefore silently dropped
every target after the first when lowering a computed `GO TO` or
arithmetic `IF`, so any analysis that consulted `controlSuccessor` to
enumerate branch targets saw only the first label.
Add `extraControlSuccessors` alongside
`controlSuccessor`. `markBranchTarget` still fills `controlSuccessor`
with the first target, but appends each subsequent distinct target to
`extraControlSuccessors`. Extend the PFT dumper to print the extra
targets after the first ("-> N, M, K"), so PFT dumps expose every branch
target.
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
Commit: 5a98e96135e223890cbf0640584e30c0db695ecf
https://github.com/llvm/llvm-project/commit/5a98e96135e223890cbf0640584e30c0db695ecf
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M flang/test/Driver/fakeflang.F
M flang/tools/CMakeLists.txt
M flang/tools/fakeflang/CMakeLists.txt
R flang/tools/fakeflang/ensure_flang_exists.cmake
M flang/tools/fakeflang/fakeflang.cpp
M flang/tools/flang-driver/CMakeLists.txt
M llvm/cmake/modules/LLVMExternalProjectUtils.cmake
Log Message:
-----------
[Flang][CMake] Use fakeflang as dispatcher (#209482)
With #203481 where `runtimes-configure` does not depend on `flang`
anymore, the following race could happen in incremental builds: While
ninja/make builds some of the libFortran*.so libraries in a
BUILD_SHARED_LIBS=ON build, CMake tries to execute flang which tries to
load the .so libraries while they are linked. This race condition can
only happen in incremental builds because before the real bin/flang is
built completely the first time, it points to fakeflang which would be
working. Only in an incremental build, would the real bin/flang already
been built created before, pointing to the currently re-built flang.
I did not think this would be possible because CMake only needs to probe
flang once and thereafter (in the incremental build) remembers the probe
result in `CMakeFiles/<version>/CMakeFortranCompiler.cmake`. CMake does
not support changing the compiler once configured and errors-out if you
try to change `CMAKE_Fortran_COMPILER`. I do not know why/when CMake is
re-probing the compiler in some incremental builds, but has been
reported to do so in #205360.
This patch avoids any replacement of build artifacts and instead decides
in fakeflang when to call real flang or to emulate the Flang
preprocessor. The decision is made based of on the FLANG_BOOTSTRAP_PROBE
environment variable that is set only in the configure step. The feature
that allows this is unfortunately only available starting in CMake 4.2.
All suppported CMake versions before CMake 4.2 use the filename
`CMakeFortranCompilerId.F`, so make the decision based on that when
using earlier versions of CMake.
Tested with CMake 3.20, 3.28, 3.31, 4.1, and 4.2.
Fixes #205360
Commit: 57ceb12780157d68f7c14d5ed8f18bc87dc768fd
https://github.com/llvm/llvm-project/commit/57ceb12780157d68f7c14d5ed8f18bc87dc768fd
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/DebugInfo/PDB/Native/LinePrinter.h
Log Message:
-----------
[DebugInfo][NFC] Fix PDB/Native/LinePrinter.h build warning -Wmicrosoft-unqualified-friend (#209715)
Fix build warning on Windows, which is error under -Werror: unqualified
friend declaration referring to type outside of the nearest enclosing
namespace is a Microsoft extension; add a nested name specifier
[-Wmicrosoft-unqualified-friend]
Commit: 5e4f44041d32234ea8227cbb2473173bd5edfc1c
https://github.com/llvm/llvm-project/commit/5e4f44041d32234ea8227cbb2473173bd5edfc1c
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/MC/AMDGPU/gfx13_asm_vds.s
Log Message:
-----------
[AMDGPU] Clean up GFX13 feature list (#208416)
GFX13 features were previously mostly inherited from GFX12/GFX1250.
- define an explicit gfx13 target parser feature list, including
gfx13-insts and cvt-pknorm-vop3-insts.
- remove transpose load F4/F6 support from gfx13 (previously copied from
gfx12)
Commit: 3faf46d218d3cb888c818b3e99d7e05b06ca68fa
https://github.com/llvm/llvm-project/commit/3faf46d218d3cb888c818b3e99d7e05b06ca68fa
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/InProcessControllerAccess.h
M orc-rt/include/orc-rt/Session.h
M orc-rt/lib/executor/InProcessControllerAccess.cpp
M orc-rt/test/unit/SessionTest.cpp
Log Message:
-----------
[orc-rt] Session::OnCallControllerReturnFn, comments. NFC. (#210035)
Rename Session::OnCallHandlerCompleteFn to
Session::OnControllerCallReturnFn and add a comment to clarify its
purpose: This callback is used to handle retured values from calls to
the controller.
Commit: 8866215f30953c7df146276ac10753de941b1fcb
https://github.com/llvm/llvm-project/commit/8866215f30953c7df146276ac10753de941b1fcb
Author: mkovacevic99 <mkovacevic at baylibre.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm-c/Orc.h
Log Message:
-----------
[Orc] Update the comment so it doesn't mention TargetTriple argument that no longer exists (#210023)
Completes the fix for the
https://github.com/llvm/llvm-project/issues/80097
Commit: 3d87de86a24d1bff2821e4eb2f2d28e58605a394
https://github.com/llvm/llvm-project/commit/3d87de86a24d1bff2821e4eb2f2d28e58605a394
Author: Philip742 <philip.wilkinson at arm.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
Log Message:
-----------
[mlir][tosa] Add support for MXFP in CONCAT (#209719)
Adds support to profile compliance for MXFP variants of CONCAT
Signed-off-by: Philip Wilkinson <philip.wilkinson at arm.com>
Commit: 18fc5a8adbe5dba7dc281bacdb149e95dc7dc1be
https://github.com/llvm/llvm-project/commit/18fc5a8adbe5dba7dc281bacdb149e95dc7dc1be
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/test/TableGen/MacroFusion.td
M llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
Log Message:
-----------
[TableGen][RISCV] Generate pre/post-RA statistics for macro fusions (#209394)
Teach `MacroFusionPredicatorEmitter` to emit `Statistic` counters
recording how often each macro fusion is matched, and wire them
up for RISC-V.
This is based on the idea in #186499, generalized so counters are
generated automatically for any target using the emitter.
Because both the pre-RA and post-RA schedulers run MacroFusion,
a single counter would conflate the two. Counters are split into
pre-RA/post-RA variants, distinguished by the `NoVRegs` property,
addressing the double-counting concern from #186499:
```cpp
STATISTIC(NumTuneLDADDFusionPreRA, "Times TuneLDADDFusion Triggered (pre-ra)");
STATISTIC(NumTuneLDADDFusionPostRA, "Times TuneLDADDFusion Triggered (post-ra)");
...
if (SecondMI.getMF()->getProperties().hasNoVRegs())
++NumTuneLDADDFusionPostRA;
else
++NumTuneLDADDFusionPreRA;
```
Besides, RISC-V counters use the `riscv-macro-fusion` debug type.
Co-authored-by: Sam Elliott <aelliott at qti.qualcomm.com>
Assisted-by: TRAE CLI (DeepSeek V4 Pro)
Commit: db7356dde8312a86e79ec0d7b7f844878a1a743c
https://github.com/llvm/llvm-project/commit/db7356dde8312a86e79ec0d7b7f844878a1a743c
Author: Petr Hosek <phosek at google.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libcxx/src/include/overridable_function.h
M libcxx/src/new.cpp
M libcxxabi/src/stdlib_new_delete.cpp
Log Message:
-----------
[libc++] Partially revert #208330 (#209928)
We found out that the new mechanism for detecting overriden functions
does not support Arm Pointer Authentication (PAuth). Addressing this
limitation is going to require changes to Clang. In the meantime, we
switched back to the old mechanism when PAuth is enabled.
Commit: 3bf897eaac63ea4e6b8c4f77d84f833f63167e3d
https://github.com/llvm/llvm-project/commit/3bf897eaac63ea4e6b8c4f77d84f833f63167e3d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/loop-invariant-gather-inst-count.ll
Log Message:
-----------
[SLP][NFC]Add a test with the non-profitable instcount check across the loops, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/210045
Commit: ee5cff53cf4f0c23254bda94c7249e4ea008d457
https://github.com/llvm/llvm-project/commit/ee5cff53cf4f0c23254bda94c7249e4ea008d457
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libsycl/unittests/mock/helpers.cpp
Log Message:
-----------
[libsycl] Fix mock error in unittest helper (#209726)
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 66e8cc5ec83d7ec5e506c53b11c1d22887c0c418
https://github.com/llvm/llvm-project/commit/66e8cc5ec83d7ec5e506c53b11c1d22887c0c418
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/or-non-negative.ll
M llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
Log Message:
-----------
[ConstraintElim] Handle (X | Y) >s -1 as X >s -1 && Y >s -1. (#209743)
InstCombine canonicalizes X >=s 0 && Y >=s 0 as (X | Y) >=s 0. Teach
ConstraintElimination to recover the signed-positive information by
looking through compares of binary ORs.
Alive2 Proof: https://alive2.llvm.org/ce/z/sqNF8M
Compile-time impact is neutral
https://llvm-compile-time-tracker.com/compare.php?from=88acd428fd72f44312408c3fb6165992fb3b043a&to=a2aa4cacb953b32d6319939b9aee3226a7294334&stat=instructions%3Au
PR: https://github.com/llvm/llvm-project/pull/209743
Commit: 6388cfc492e82702dfc1aa965adab7e85c7ad3d8
https://github.com/llvm/llvm-project/commit/6388cfc492e82702dfc1aa965adab7e85c7ad3d8
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/reduction.ll
Log Message:
-----------
[AMDGPU] Add missing FMF flags in tests (NFC) (#210055)
The flags should be on the select, not the fcmp for nsz to have
any effect.
Commit: 424fec2368d615dff78b4167e78e9bbb06fc4214
https://github.com/llvm/llvm-project/commit/424fec2368d615dff78b4167e78e9bbb06fc4214
Author: Jessica Clarke <jrtc27 at jrtc27.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/Analysis/AliasSet/memset.ll
Log Message:
-----------
[NFC][test][AliasSet] Canonicalise memset.ll's overload suffices (#210059)
The second overload suffix here corresponds to the type of the length,
the third argument, which is an i64 not an i32. Canonicalise this to
avoid confusion from inconsistency.
Whilst here, fix the whitespace used to align the arguments in the
intrinsic declarations, a remnant of losing the two characters in "i8"
when migrating to opaque pointers.
Fixes: 9f0916129024 ("[AST] Add test coverage of memsets")
Fixes: ac924305793c ("[AliasSet] Convert tests to opaque pointers
(NFC)")
Commit: 006d13e206401545c011028d85749071acdc5326
https://github.com/llvm/llvm-project/commit/006d13e206401545c011028d85749071acdc5326
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M offload/plugins-nextgen/level_zero/include/L0Kernel.h
M offload/plugins-nextgen/level_zero/include/L0Options.h
M offload/plugins-nextgen/level_zero/src/L0Options.cpp
M offload/plugins-nextgen/level_zero/src/L0Queue.cpp
Log Message:
-----------
[OFFLOAD][L0][NFC] Cleanup dead code (#210060)
As we have done several refactorings lately, some dead code/data was
left behind inadvertedly. This is just cleaning it up.
Commit: 6ba12f1878384fa0d5be092b511f67e7e808772b
https://github.com/llvm/llvm-project/commit/6ba12f1878384fa0d5be092b511f67e7e808772b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
Log Message:
-----------
[X86] fold-signbit-reduction-cmp.ll - test for each x86-64 cpu level (#210051)
Commit: 26c200d88e720fa88e8692ace13a493696ac591f
https://github.com/llvm/llvm-project/commit/26c200d88e720fa88e8692ace13a493696ac591f
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN sin builtins (#197784)
Adds codegen for the following AMDGCN sin builtins:
- __builtin_amdgcn_sinf (float)
- __builtin_amdgcn_sinh (half)
- __builtin_amdgcn_sin_bf16 (bfloat16)
These are lowered to the corresponding `llvm.amdgcn.sin` intrinsic.
Commit: 8739d89c4c2475eefc4638882311515fc67f9f9b
https://github.com/llvm/llvm-project/commit/8739d89c4c2475eefc4638882311515fc67f9f9b
Author: Yuan Suo <suoyuan666 at s5n.xyz>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/test/Sema/LifetimeSafety/invalidations.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Introduce buildOriginFlowChain to use-after-invalidation (#208891)
After completing the implementation of `buildOriginFlowChain`, we should
integrate it into the remaining diagnostics. I started with
`use-after-invalidation` because there is already an overload of
`buildOriginFlowChain` for `UseFact`.
While testing, I noticed the following diagnostics:
```txt
test.cpp:9:23: note: result of call to 'begin<std::vector<int>>' aliases the storage of parameter 'v'
9 | auto it = std::find(std::begin(v), std::end(v), 3); // expected-warning {{parameter 'v' is later invalidated}} \
| ^~~~~~~~~~~~~
test.cpp:9:13: note: result of call to 'find<__gnu_cxx::__normal_iterator<int *, std::vector<int>>, int>' aliases the storage of parameter 'v'
9 | auto it = std::find(std::begin(v), std::end(v), 3); // expected-warning {{parameter 'v' is later invalidated}} \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```
I think these diagnostics could be made clearer, but I'd prefer to
address that in a separate PR.
---------
Signed-off-by: Yuan Suo <suoyuan666 at s5n.xyz>
Commit: 19595357e32b36383a025fddaaf8c38f90658b7b
https://github.com/llvm/llvm-project/commit/19595357e32b36383a025fddaaf8c38f90658b7b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vpdpwssd.ll
Log Message:
-----------
[X86] combineAdd - remove unnecessary add(a,concat(vpmaddwd(x,y),vpmaddwd(z,w))) -> vpdpwssd(a,concat(x,z),concat(y,w)) fold (#209838)
We already handle vpmaddwd concatenation in combineConcatVectorOps - but
512-bit vpmaddwd is only available on BWI targets, which was missing
from the tests
Technically if there's a target that has AVX512VNNI but not BWI, then
this fold would be useful, but there's no such target and there's a
limit to "what if" optimisations we really need.
A small attempt at cleaning out some not very useful code from
X86ISelLowering.cpp - I'm intending to do a lot more of this for 24.x / #143088
Commit: e3d3b3b0cf3672480d6f781a9726cec1e7983d14
https://github.com/llvm/llvm-project/commit/e3d3b3b0cf3672480d6f781a9726cec1e7983d14
Author: DylanFleming-arm <85629460+DylanFleming-arm at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/src/__support/CPP/CMakeLists.txt
M libc/src/__support/CPP/simd.h
M libc/src/__support/mathvec/CMakeLists.txt
A libc/src/__support/mathvec/acosf.h
A libc/src/__support/mathvec/acoshf.h
A libc/src/__support/mathvec/acospif.h
A libc/src/__support/mathvec/asinf.h
A libc/src/__support/mathvec/asinhf.h
A libc/src/__support/mathvec/asinpif.h
A libc/src/__support/mathvec/atanf.h
A libc/src/__support/mathvec/atanhf.h
A libc/src/__support/mathvec/cbrtf.h
M libc/src/__support/mathvec/common_constants.h
A libc/src/__support/mathvec/cosf.h
A libc/src/__support/mathvec/coshf.h
A libc/src/__support/mathvec/cospif.h
A libc/src/__support/mathvec/erff.h
A libc/src/__support/mathvec/exp10f.h
A libc/src/__support/mathvec/exp10m1f.h
A libc/src/__support/mathvec/exp2f.h
A libc/src/__support/mathvec/exp2m1f.h
M libc/src/__support/mathvec/expf.h
M libc/src/__support/mathvec/expf_utils.h
A libc/src/__support/mathvec/expm1f.h
A libc/src/__support/mathvec/log10f.h
A libc/src/__support/mathvec/log1pf.h
A libc/src/__support/mathvec/log2f.h
A libc/src/__support/mathvec/logf.h
A libc/src/__support/mathvec/rsqrtf.h
A libc/src/__support/mathvec/sinf.h
A libc/src/__support/mathvec/sinhf.h
A libc/src/__support/mathvec/sinpif.h
A libc/src/__support/mathvec/sqrtf.h
A libc/src/__support/mathvec/tanf.h
A libc/src/__support/mathvec/tanhf.h
A libc/src/__support/mathvec/tanpif.h
M libc/src/mathvec/CMakeLists.txt
A libc/src/mathvec/abi_prefix.h
A libc/src/mathvec/acosf.h
A libc/src/mathvec/acoshf.h
A libc/src/mathvec/acospif.h
A libc/src/mathvec/asinf.h
A libc/src/mathvec/asinhf.h
A libc/src/mathvec/asinpif.h
A libc/src/mathvec/atanf.h
A libc/src/mathvec/atanhf.h
A libc/src/mathvec/cbrtf.h
A libc/src/mathvec/cosf.h
A libc/src/mathvec/coshf.h
A libc/src/mathvec/cospif.h
A libc/src/mathvec/erff.h
A libc/src/mathvec/exp10f.h
A libc/src/mathvec/exp10m1f.h
A libc/src/mathvec/exp2f.h
A libc/src/mathvec/exp2m1f.h
M libc/src/mathvec/expf.h
A libc/src/mathvec/expm1f.h
M libc/src/mathvec/generic/CMakeLists.txt
A libc/src/mathvec/generic/acosf.cpp
A libc/src/mathvec/generic/acoshf.cpp
A libc/src/mathvec/generic/acospif.cpp
A libc/src/mathvec/generic/asinf.cpp
A libc/src/mathvec/generic/asinhf.cpp
A libc/src/mathvec/generic/asinpif.cpp
A libc/src/mathvec/generic/atanf.cpp
A libc/src/mathvec/generic/atanhf.cpp
A libc/src/mathvec/generic/cbrtf.cpp
A libc/src/mathvec/generic/cosf.cpp
A libc/src/mathvec/generic/coshf.cpp
A libc/src/mathvec/generic/cospif.cpp
A libc/src/mathvec/generic/erff.cpp
A libc/src/mathvec/generic/exp10f.cpp
A libc/src/mathvec/generic/exp10m1f.cpp
A libc/src/mathvec/generic/exp2f.cpp
A libc/src/mathvec/generic/exp2m1f.cpp
M libc/src/mathvec/generic/expf.cpp
A libc/src/mathvec/generic/expm1f.cpp
A libc/src/mathvec/generic/log10f.cpp
A libc/src/mathvec/generic/log1pf.cpp
A libc/src/mathvec/generic/log2f.cpp
A libc/src/mathvec/generic/logf.cpp
A libc/src/mathvec/generic/rsqrtf.cpp
A libc/src/mathvec/generic/sinf.cpp
A libc/src/mathvec/generic/sinhf.cpp
A libc/src/mathvec/generic/sinpif.cpp
A libc/src/mathvec/generic/sqrtf.cpp
A libc/src/mathvec/generic/tanf.cpp
A libc/src/mathvec/generic/tanhf.cpp
A libc/src/mathvec/generic/tanpif.cpp
A libc/src/mathvec/log10f.h
A libc/src/mathvec/log1pf.h
A libc/src/mathvec/log2f.h
A libc/src/mathvec/logf.h
A libc/src/mathvec/rsqrtf.h
A libc/src/mathvec/sinf.h
A libc/src/mathvec/sinhf.h
A libc/src/mathvec/sinpif.h
A libc/src/mathvec/sqrtf.h
A libc/src/mathvec/tanf.h
A libc/src/mathvec/tanhf.h
A libc/src/mathvec/tanpif.h
M libc/test/src/mathvec/CMakeLists.txt
A libc/test/src/mathvec/UnitTestWrappers.h
A libc/test/src/mathvec/acosf_test.cpp
A libc/test/src/mathvec/acoshf_test.cpp
A libc/test/src/mathvec/acospif_test.cpp
A libc/test/src/mathvec/asinf_test.cpp
A libc/test/src/mathvec/asinhf_test.cpp
A libc/test/src/mathvec/asinpif_test.cpp
A libc/test/src/mathvec/atanf_test.cpp
A libc/test/src/mathvec/atanhf_test.cpp
A libc/test/src/mathvec/cbrtf_test.cpp
A libc/test/src/mathvec/cosf_test.cpp
A libc/test/src/mathvec/coshf_test.cpp
A libc/test/src/mathvec/cospif_test.cpp
A libc/test/src/mathvec/erff_test.cpp
M libc/test/src/mathvec/exhaustive/CMakeLists.txt
A libc/test/src/mathvec/exhaustive/acosf_test.cpp
A libc/test/src/mathvec/exhaustive/acoshf_test.cpp
A libc/test/src/mathvec/exhaustive/acospif_test.cpp
A libc/test/src/mathvec/exhaustive/asinf_test.cpp
A libc/test/src/mathvec/exhaustive/asinhf_test.cpp
A libc/test/src/mathvec/exhaustive/asinpif_test.cpp
A libc/test/src/mathvec/exhaustive/atanf_test.cpp
A libc/test/src/mathvec/exhaustive/atanhf_test.cpp
A libc/test/src/mathvec/exhaustive/cbrtf_test.cpp
A libc/test/src/mathvec/exhaustive/cosf_test.cpp
A libc/test/src/mathvec/exhaustive/coshf_test.cpp
A libc/test/src/mathvec/exhaustive/cospif_test.cpp
A libc/test/src/mathvec/exhaustive/erff_test.cpp
M libc/test/src/mathvec/exhaustive/exhaustive_test.h
A libc/test/src/mathvec/exhaustive/exp10f_test.cpp
A libc/test/src/mathvec/exhaustive/exp10m1f_test.cpp
A libc/test/src/mathvec/exhaustive/exp2f_test.cpp
A libc/test/src/mathvec/exhaustive/exp2m1f_test.cpp
M libc/test/src/mathvec/exhaustive/expf_test.cpp
A libc/test/src/mathvec/exhaustive/expm1f_test.cpp
A libc/test/src/mathvec/exhaustive/log10f_test.cpp
A libc/test/src/mathvec/exhaustive/log1pf_test.cpp
A libc/test/src/mathvec/exhaustive/log2f_test.cpp
A libc/test/src/mathvec/exhaustive/logf_test.cpp
A libc/test/src/mathvec/exhaustive/rsqrtf_test.cpp
A libc/test/src/mathvec/exhaustive/sinf_test.cpp
A libc/test/src/mathvec/exhaustive/sinhf_test.cpp
A libc/test/src/mathvec/exhaustive/sinpif_test.cpp
A libc/test/src/mathvec/exhaustive/sqrtf_test.cpp
A libc/test/src/mathvec/exhaustive/tanf_test.cpp
A libc/test/src/mathvec/exhaustive/tanhf_test.cpp
A libc/test/src/mathvec/exhaustive/tanpif_test.cpp
A libc/test/src/mathvec/exp10f_test.cpp
A libc/test/src/mathvec/exp10m1f_test.cpp
A libc/test/src/mathvec/exp2f_test.cpp
A libc/test/src/mathvec/exp2m1f_test.cpp
M libc/test/src/mathvec/expf_test.cpp
A libc/test/src/mathvec/expm1f_test.cpp
A libc/test/src/mathvec/log10f_test.cpp
A libc/test/src/mathvec/log1pf_test.cpp
A libc/test/src/mathvec/log2f_test.cpp
A libc/test/src/mathvec/logf_test.cpp
A libc/test/src/mathvec/rsqrtf_test.cpp
A libc/test/src/mathvec/sinf_test.cpp
A libc/test/src/mathvec/sinhf_test.cpp
A libc/test/src/mathvec/sinpif_test.cpp
A libc/test/src/mathvec/sqrtf_test.cpp
A libc/test/src/mathvec/tanf_test.cpp
A libc/test/src/mathvec/tanhf_test.cpp
A libc/test/src/mathvec/tanpif_test.cpp
Log Message:
-----------
[libc][mathvec] Add loop over scalar for unary FP32 (#199273)
Adds all FP32 unary functions currently supported in scalar LLVM LIBM to
LIBMVEC as loop over scalars.
Includes some cleanup of existing mathvec testing infrastructure
Commit: 1cb7e838cd47ecad4050948c0c907ecb1f466ac3
https://github.com/llvm/llvm-project/commit/1cb7e838cd47ecad4050948c0c907ecb1f466ac3
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[AMDGPU] Simplify some isVALU calls. NFC. (#210057)
Commit: beee8c8708c1013bd9c1e94f820c68c2dfa0bf64
https://github.com/llvm/llvm-project/commit/beee8c8708c1013bd9c1e94f820c68c2dfa0bf64
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M .github/new-prs-labeler.yml
M bolt/lib/Core/BinaryContext.cpp
A bolt/test/X86/jump-table-failed-reanalysis.s
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/unittests/PrerequisiteModulesTest.cpp
M clang/bindings/python/tests/cindex/test_diagnostics.py
A clang/docs/AMDGPUSupport.md
R clang/docs/AMDGPUSupport.rst
A clang/docs/APINotes.md
R clang/docs/APINotes.rst
A clang/docs/AllocToken.md
R clang/docs/AllocToken.rst
A clang/docs/BoundsSafety.md
R clang/docs/BoundsSafety.rst
A clang/docs/BoundsSafetyAdoptionGuide.md
R clang/docs/BoundsSafetyAdoptionGuide.rst
A clang/docs/BoundsSafetyImplPlans.md
R clang/docs/BoundsSafetyImplPlans.rst
A clang/docs/CIR/index.md
R clang/docs/CIR/index.rst
A clang/docs/CXXTypeAwareAllocators.md
R clang/docs/CXXTypeAwareAllocators.rst
A clang/docs/ClangPlugins.md
R clang/docs/ClangPlugins.rst
A clang/docs/CommandGuide/index.md
R clang/docs/CommandGuide/index.rst
A clang/docs/ControlFlowIntegrity.md
R clang/docs/ControlFlowIntegrity.rst
A clang/docs/DebuggingCoroutines.md
R clang/docs/DebuggingCoroutines.rst
A clang/docs/ExternalClangExamples.md
R clang/docs/ExternalClangExamples.rst
A clang/docs/FAQ.md
R clang/docs/FAQ.rst
M clang/docs/HIPSupport.md
A clang/docs/IntroductionToTheClangAST.md
R clang/docs/IntroductionToTheClangAST.rst
A clang/docs/LibClang.md
R clang/docs/LibClang.rst
A clang/docs/LibFormat.md
R clang/docs/LibFormat.rst
A clang/docs/LibTooling.md
R clang/docs/LibTooling.rst
A clang/docs/RISCVSupport.md
R clang/docs/RISCVSupport.rst
M clang/docs/ReleaseNotes.md
A clang/docs/Tooling.md
R clang/docs/Tooling.rst
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/PropertiesBase.td
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Basic/Diagnostic.td
M clang/include/clang/Basic/DiagnosticIDs.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenCLExtensions.def
M clang/include/clang/Frontend/SSAFOptions.h
M clang/include/clang/Options/Options.td
M clang/include/clang/Sema/ExternalSemaSource.h
M clang/include/clang/Sema/MultiplexExternalSemaSource.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Serialization/ASTReader.h
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ByteCode/Record.cpp
M clang/lib/AST/ByteCode/Record.h
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Basic/DiagnosticIDs.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMIR.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysis/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
M clang/lib/Sema/MultiplexExternalSemaSource.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaBase.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/StaticAnalyzer/Checkers/MPI-Checker/MPIFunctionClassifier.cpp
M clang/test/AST/ByteCode/builtin-object-size.cpp
M clang/test/AST/ByteCode/cxx11.cpp
A clang/test/AST/ByteCode/virtual-bases-codegen.cpp
A clang/test/AST/ByteCode/virtual-bases.cpp
M clang/test/AST/HLSL/HLSLControlFlowHint.hlsl
R clang/test/AST/HLSL/Texture2D-AST.hlsl
R clang/test/AST/HLSL/Texture2D-scalar-AST.hlsl
R clang/test/AST/HLSL/Texture2D-shorthand-AST.hlsl
R clang/test/AST/HLSL/Texture2D-vector-AST.hlsl
R clang/test/AST/HLSL/Texture2DArray-scalar-AST.hlsl
R clang/test/AST/HLSL/Texture2DArray-shorthand-AST.hlsl
R clang/test/AST/HLSL/Texture2DArray-vector-AST.hlsl
A clang/test/AST/HLSL/Textures-AST.hlsl
A clang/test/AST/HLSL/Textures-scalar-AST.hlsl
A clang/test/AST/HLSL/Textures-shorthand-AST.hlsl
A clang/test/AST/HLSL/Textures-vector-AST.hlsl
M clang/test/AST/HLSL/matrix-alias.hlsl
M clang/test/AST/HLSL/matrix-constructors.hlsl
M clang/test/AST/HLSL/matrix-elementexpr-tree-transform.hlsl
M clang/test/AST/HLSL/matrix-general-initializer.hlsl
M clang/test/AST/HLSL/matrix-member-access-scalar.hlsl
M clang/test/AST/HLSL/matrix-member-access-swizzle.hlsl
M clang/test/AST/HLSL/resources-in-structs-errors.hlsl
M clang/test/AST/HLSL/resources-in-structs.hlsl
M clang/test/AST/HLSL/vector-alias.hlsl
M clang/test/AST/HLSL/vector-constructors.hlsl
M clang/test/AST/HLSL/vk.spec-constant.usage.hlsl
M clang/test/Analysis/MPIMock.h
A clang/test/Analysis/Scalable/PointerFlow/system-header-opt-out.cpp
M clang/test/Analysis/Scalable/help.cpp
M clang/test/Analysis/mpichecker.cpp
A clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zihintntl.c
M clang/test/CIR/CodeGenBuiltins/builtin-call.cpp
M clang/test/CIR/CodeGenBuiltins/builtins-elementwise.c
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
M clang/test/CIR/CodeGenHLSL/matrix-element-expr-load.hlsl
M clang/test/CXX/drs/cwg16xx.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg6xx.cpp
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
M clang/test/CodeGen/attr-nomerge.cpp
A clang/test/CodeGen/builtin-trap.c
M clang/test/CodeGen/c11atomics.c
M clang/test/CodeGen/pr53127.cpp
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
M clang/test/CodeGenCXX/microsoft-abi-byval-vararg.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
M clang/test/CodeGenCXX/trap-fnattr.cpp
M clang/test/CodeGenCXX/vararg-non-pod.cpp
M clang/test/CodeGenHLSL/BasicFeatures/frem_modulo.hlsl
M clang/test/CodeGenHLSL/builtins/AllMemoryBarrier.hlsl
M clang/test/CodeGenHLSL/builtins/AllMemoryBarrierWithGroupSync.hlsl
M clang/test/CodeGenHLSL/builtins/DeviceMemoryBarrier.hlsl
M clang/test/CodeGenHLSL/builtins/DeviceMemoryBarrierWithGroupSync.hlsl
M clang/test/CodeGenHLSL/builtins/GroupMemoryBarrier.hlsl
M clang/test/CodeGenHLSL/builtins/GroupMemoryBarrierWithGroupSync.hlsl
M clang/test/CodeGenHLSL/builtins/InterlockedAdd.hlsl
M clang/test/CodeGenHLSL/builtins/InterlockedOr.hlsl
M clang/test/CodeGenHLSL/builtins/QuadReadAcrossDiagonal.hlsl
M clang/test/CodeGenHLSL/builtins/QuadReadAcrossX.hlsl
M clang/test/CodeGenHLSL/builtins/QuadReadAcrossY.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveAllEqual.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveAllTrue.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveAnyTrue.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBallot.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBitAnd.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBitXor.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveCountBits.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveMax.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveMin.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveProduct.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveSum.hlsl
M clang/test/CodeGenHLSL/builtins/WavePrefixCountBits.hlsl
M clang/test/CodeGenHLSL/builtins/WavePrefixProduct.hlsl
M clang/test/CodeGenHLSL/builtins/WavePrefixSum.hlsl
M clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
M clang/test/CodeGenHLSL/builtins/acos-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/acos.hlsl
M clang/test/CodeGenHLSL/builtins/all.hlsl
M clang/test/CodeGenHLSL/builtins/any.hlsl
M clang/test/CodeGenHLSL/builtins/asdouble.hlsl
M clang/test/CodeGenHLSL/builtins/asin-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/asin.hlsl
M clang/test/CodeGenHLSL/builtins/atan-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan.hlsl
M clang/test/CodeGenHLSL/builtins/atan2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan2-overloads_mat.hlsl
M clang/test/CodeGenHLSL/builtins/atan2.hlsl
M clang/test/CodeGenHLSL/builtins/atan2_mat.hlsl
M clang/test/CodeGenHLSL/builtins/clamp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/clamp.hlsl
M clang/test/CodeGenHLSL/builtins/clip.hlsl
M clang/test/CodeGenHLSL/builtins/cosh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/cosh.hlsl
M clang/test/CodeGenHLSL/builtins/cross.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-coarse-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-coarse.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-fine-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-fine.hlsl
M clang/test/CodeGenHLSL/builtins/ddx.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-coarse-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-coarse.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-fine-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-fine.hlsl
M clang/test/CodeGenHLSL/builtins/ddy.hlsl
M clang/test/CodeGenHLSL/builtins/degrees-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/degrees.hlsl
M clang/test/CodeGenHLSL/builtins/distance.hlsl
M clang/test/CodeGenHLSL/builtins/dot.hlsl
M clang/test/CodeGenHLSL/builtins/dot2add.hlsl
M clang/test/CodeGenHLSL/builtins/f16tof32-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f16tof32.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16.hlsl
M clang/test/CodeGenHLSL/builtins/faceforward.hlsl
M clang/test/CodeGenHLSL/builtins/firstbithigh.hlsl
M clang/test/CodeGenHLSL/builtins/firstbitlow.hlsl
M clang/test/CodeGenHLSL/builtins/fma.hlsl
M clang/test/CodeGenHLSL/builtins/fmod.hlsl
M clang/test/CodeGenHLSL/builtins/frac-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/frac.hlsl
M clang/test/CodeGenHLSL/builtins/isinf-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/isinf.hlsl
M clang/test/CodeGenHLSL/builtins/isnan.hlsl
M clang/test/CodeGenHLSL/builtins/length.hlsl
M clang/test/CodeGenHLSL/builtins/lerp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/lerp.hlsl
M clang/test/CodeGenHLSL/builtins/mad.hlsl
M clang/test/CodeGenHLSL/builtins/normalize-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/normalize.hlsl
M clang/test/CodeGenHLSL/builtins/radians-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/radians.hlsl
M clang/test/CodeGenHLSL/builtins/rcp.hlsl
M clang/test/CodeGenHLSL/builtins/reflect.hlsl
M clang/test/CodeGenHLSL/builtins/refract.hlsl
M clang/test/CodeGenHLSL/builtins/rsqrt-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/rsqrt.hlsl
M clang/test/CodeGenHLSL/builtins/sign.hlsl
M clang/test/CodeGenHLSL/builtins/sinh.hlsl
M clang/test/CodeGenHLSL/builtins/smoothstep.hlsl
M clang/test/CodeGenHLSL/builtins/step-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/step.hlsl
M clang/test/CodeGenHLSL/builtins/tan-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/tan.hlsl
M clang/test/CodeGenHLSL/builtins/tanh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/tanh.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-methods-ps.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-CalculateLevelOfDetail.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Gather.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-GetDimensions.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Load.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Mips.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Sample.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleBias.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleCmp.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleCmpLevelZero.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleGrad.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleLevel.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Subscript.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-default-explicit-binding.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-default.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-shorthand-contexts.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-CalculateLevelOfDetail.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Gather.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Load.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Mips.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Sample.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleBias.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleCmp.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleCmpLevelZero.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleGrad.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleLevel.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Subscript.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-default-explicit-binding.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-default.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-shorthand-contexts.hlsl
A clang/test/CodeGenHLSL/resources/Textures-CalculateLevelOfDetail.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Gather.hlsl
A clang/test/CodeGenHLSL/resources/Textures-GetDimensions.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Load.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Mips.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Sample.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleBias.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleCmp.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleCmpLevelZero.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleGrad.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleLevel.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Subscript.hlsl
A clang/test/CodeGenHLSL/resources/Textures-default-explicit-binding.hlsl
A clang/test/CodeGenHLSL/resources/Textures-default.hlsl
A clang/test/CodeGenHLSL/resources/Textures-shorthand-contexts.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_geps.hlsl
M clang/test/CodeGenHLSL/semantics/semantic.explicit-mix-builtin.vs.hlsl
M clang/test/DebugInfo/CXX/verbose-trap.cpp
A clang/test/Driver/Inputs/resource_dir_with_amdgpu_per_target_subdir/lib/amdgpu-amd-amdhsa/libclang_rt.profile.a
M clang/test/Driver/amdgpu-toolchain.c
M clang/test/Driver/dxc_hlsl-rootsig-ver.hlsl
M clang/test/Driver/openmp-invalid-target-id.c
M clang/test/Driver/spirv-amd-toolchain.c
M clang/test/Headers/gpuintrin.c
A clang/test/Misc/amdgcn.unsupported_core_3.1.cl
M clang/test/OpenMP/spirv_target_codegen_noexceptions.cpp
A clang/test/PCH/unused-local-typedef-determinism.cpp
M clang/test/ParserHLSL/access_specifiers.hlsl
M clang/test/ParserHLSL/hlsl_contained_type_attr.hlsl
M clang/test/ParserHLSL/hlsl_contained_type_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_is_array_attr.hlsl
M clang/test/ParserHLSL/hlsl_is_array_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_is_rov_attr.hlsl
M clang/test/ParserHLSL/hlsl_is_rov_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_raw_buffer_attr.hlsl
M clang/test/ParserHLSL/hlsl_raw_buffer_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_resource_class_attr.hlsl
M clang/test/ParserHLSL/hlsl_resource_class_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_resource_dimension_attr.hlsl
M clang/test/ParserHLSL/hlsl_resource_dimension_attr_error.hlsl
M clang/test/ParserHLSL/semantic_parsing.hlsl
M clang/test/ParserHLSL/semantic_parsing_define.hlsl
M clang/test/Sema/LifetimeSafety/invalidations.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
M clang/test/SemaCXX/enable_if.cpp
A clang/test/SemaCXX/warn-unused-local-typedef-deterministic-order.cpp
M clang/test/SemaHLSL/Availability/attr-deprecated.hlsl
M clang/test/SemaHLSL/BuiltIns/binary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/fma-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/matrix-constructors-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/ternary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/unary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/vec-scalar-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/vector-constructors-errors.hlsl
M clang/test/SemaHLSL/Language/InitIncompleteArrays.hlsl
M clang/test/SemaHLSL/Language/InitLists.hlsl
M clang/test/SemaHLSL/Language/NoVirtual.hlsl
M clang/test/SemaHLSL/Language/OutputParameters.hlsl
M clang/test/SemaHLSL/Language/TemplateOutArg.hlsl
M clang/test/SemaHLSL/Resources/ConstantBuffers.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-CalculateLevelOfDetail.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-GetDimensions.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-Load-errors.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleBias.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleCmp.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleCmpLevelZero.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleGrad.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleLevel.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-Sema.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-Subscript.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-CalculateLevelOfDetail.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-GetDimensions.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleBias.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleCmp.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleCmpLevelZero.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleGrad.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleLevel.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-Sema.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-Subscript.hlsl
A clang/test/SemaHLSL/Resources/Textures-CalculateLevelOfDetail.hlsl
A clang/test/SemaHLSL/Resources/Textures-GetDimensions.hlsl
A clang/test/SemaHLSL/Resources/Textures-Load-errors.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleBias.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleCmp.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleCmpLevelZero.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleGrad.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleLevel.hlsl
A clang/test/SemaHLSL/Resources/Textures-Sema.hlsl
A clang/test/SemaHLSL/Resources/Textures-Subscript.hlsl
M clang/test/SemaHLSL/Semantics/semantic.explicit-mix-builtin-vs.hlsl
M clang/test/SemaHLSL/Semantics/semantic.explicit-mix-location-2.hlsl
M clang/test/SemaHLSL/Semantics/semantic.explicit-mix-location.hlsl
M clang/test/SemaHLSL/Semantics/valid_entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/vertexid.vs.hlsl
R clang/test/SemaHLSL/Texture2D-Gather.hlsl
R clang/test/SemaHLSL/Texture2D-GatherCmp-Vulkan.hlsl
R clang/test/SemaHLSL/Texture2D-mips-errors.hlsl
R clang/test/SemaHLSL/Texture2DArray-Gather.hlsl
R clang/test/SemaHLSL/Texture2DArray-GatherCmp-Vulkan.hlsl
R clang/test/SemaHLSL/Texture2DArray-mips-errors.hlsl
A clang/test/SemaHLSL/Textures-Gather.hlsl
A clang/test/SemaHLSL/Textures-GatherCmp-Vulkan.hlsl
A clang/test/SemaHLSL/Textures-mips-errors.hlsl
M clang/test/SemaHLSL/Types/short-errors.hlsl
M clang/test/SemaHLSL/entry_shader.hlsl
M clang/test/SemaHLSL/num_threads.hlsl
M clang/test/SemaHLSL/prohibit_reference.hlsl
M clang/test/SemaHLSL/vk.spec-constant.error.hlsl
M clang/test/SemaOpenCL/extension-version.cl
M clang/test/SemaTemplate/class-template-spec.cpp
M clang/test/lit.cfg.py
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/www/cxx_status.html
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/cmake/base-config-ix.cmake
M compiler-rt/cmake/builtin-config-ix.cmake
M compiler-rt/lib/asan/asan_interceptors.cpp
M compiler-rt/lib/builtins/CMakeLists.txt
M compiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
M compiler-rt/lib/tsan/rtl/tsan_platform.h
M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
A compiler-rt/test/msan/Linux/syscalls_setgroups.cpp
M compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
M cross-project-tests/CMakeLists.txt
A cross-project-tests/dtlto/remote-options.test
M flang-rt/lib/runtime/cudadevice.f90
M flang/include/flang/Evaluate/call.h
M flang/include/flang/Evaluate/fold.h
M flang/include/flang/Evaluate/shape.h
M flang/include/flang/Evaluate/traverse.h
M flang/include/flang/Evaluate/type.h
M flang/include/flang/Lower/OpenMP.h
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Lower/Support/ReductionProcessor.h
M flang/include/flang/Semantics/expression.h
M flang/include/flang/Semantics/openmp-utils.h
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Evaluate/call.cpp
M flang/lib/Evaluate/characteristics.cpp
M flang/lib/Evaluate/fold-implementation.h
M flang/lib/Evaluate/fold.cpp
M flang/lib/Evaluate/formatting.cpp
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/shape.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Evaluate/type.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Lower/Support/Utils.cpp
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/check-omp-variant.cpp
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/mod-file.h
M flang/lib/Semantics/openmp-utils.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Support/Fortran-features.cpp
M flang/test/Driver/fakeflang.F
A flang/test/Evaluate/fold-conditional-arg.f90
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-constructor.f90
A flang/test/Fir/CUDA/cuda-register-allocator-0.f90
A flang/test/Fir/CUDA/cuda-register-allocator-1.f90
M flang/test/Integration/OpenMP/copyprivate.f90
M flang/test/Integration/OpenMP/private-global.f90
M flang/test/Lower/CUDA/cuda-implicit-managed-alloc.cuf
M flang/test/Lower/CUDA/cuda-init.cuf
M flang/test/Lower/OpenMP/DelayedPrivatization/target-teams-distribute-private-adjustable-array.f90
A flang/test/Lower/OpenMP/Todo/declare-reduction-allocatable-trivial.f90
R flang/test/Lower/OpenMP/Todo/declare-reduction-operator-multiple-types.f90
R flang/test/Lower/OpenMP/Todo/declare-reduction-operator-use-assoc.f90
R flang/test/Lower/OpenMP/Todo/multiple-types-declare_reduction.f90
R flang/test/Lower/OpenMP/Todo/taskwait-depend.f90
M flang/test/Lower/OpenMP/copyprivate.f90
M flang/test/Lower/OpenMP/declare-reduction-character-allocatable.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-component.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-defined-assign.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-rhs-call.f90
M flang/test/Lower/OpenMP/declare-reduction-intrinsic-op.f90
A flang/test/Lower/OpenMP/declare-reduction-intrinsic-same-name-different-scope.f90
M flang/test/Lower/OpenMP/declare-reduction-logical-init.f90
A flang/test/Lower/OpenMP/declare-reduction-merge-hermetic.f90
A flang/test/Lower/OpenMP/declare-reduction-merge-version-skew.f90
A flang/test/Lower/OpenMP/declare-reduction-name-type-token-collision.f90
A flang/test/Lower/OpenMP/declare-reduction-named-renamed.f90
A flang/test/Lower/OpenMP/declare-reduction-named-separate-rename.f90
A flang/test/Lower/OpenMP/declare-reduction-named-use-assoc.f90
M flang/test/Lower/OpenMP/declare-reduction-no-initializer-derived.f90
M flang/test/Lower/OpenMP/declare-reduction-no-initializer-intrinsic.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-collide.f90
M flang/test/Lower/OpenMP/declare-reduction-operator-derived.f90
M flang/test/Lower/OpenMP/declare-reduction-operator-host-assoc.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-merged.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-multiple-types.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-renamed.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-collide-unused.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-combiners.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-hermetic.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-intrinsic-all.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-intrinsic-collide.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-intrinsic.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-multitype-partial.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-reexport.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-remerge.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-rename-remerge.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-submodule.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-unused-unsupported.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-use-assoc.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-use-only-nonreduction.f90
M flang/test/Lower/OpenMP/declare-reduction-operator.f90
M flang/test/Lower/OpenMP/declare-reduction-same-name-different-scope.f90
A flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic-multiple-types.f90
A flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic-separate.f90
A flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic-use-assoc.f90
M flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic.f90
A flang/test/Lower/OpenMP/declare-reduction-special-separate-reexport.f90
M flang/test/Lower/OpenMP/declare-reduction-target-intrinsic.f90
M flang/test/Lower/OpenMP/delayed-privatization-array.f90
M flang/test/Lower/OpenMP/lastprivate-equivalence.f90
M flang/test/Lower/OpenMP/loop-directive.f90
A flang/test/Lower/OpenMP/multiple-types-declare_reduction.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-combsub.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-derivedtype.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-initsub.f90
M flang/test/Lower/OpenMP/omp-declare-reduction.f90
M flang/test/Lower/OpenMP/parallel-private-clause.f90
A flang/test/Lower/OpenMP/private-array-boxing.f90
M flang/test/Lower/OpenMP/private-commonblock.f90
A flang/test/Lower/OpenMP/taskwait-depend.f90
M flang/test/Lower/do_concurrent_local_assoc_entity.f90
A flang/test/Lower/pre-fir-tree-multiway-branch.f90
M flang/test/Lower/pre-fir-tree02.f90
A flang/test/Semantics/OpenMP/declare-reduction-ambiguous.f90
M flang/test/Semantics/OpenMP/metadirective-loop-applicability.f90
M flang/test/Semantics/OpenMP/metadirective-loop-nest.f90
M flang/test/Semantics/conditional-arg.f90
M flang/tools/CMakeLists.txt
M flang/tools/bbc/bbc.cpp
M flang/tools/fakeflang/CMakeLists.txt
R flang/tools/fakeflang/ensure_flang_exists.cmake
M flang/tools/fakeflang/fakeflang.cpp
M flang/tools/flang-driver/CMakeLists.txt
M flang/unittests/Semantics/OpenMPUtils.cpp
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/stdfix.rst
M libc/hdr/CMakeLists.txt
A libc/hdr/sys_select_macros.h
A libc/hdr/sys_wait_macros.h
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/fd_set.h
A libc/hdr/types/struct_rusage.h
A libc/hdr/types/struct_utsname.h
M libc/include/llvm-libc-macros/netinet-in-macros.h
M libc/include/stdfix.yaml
M libc/src/__support/CPP/CMakeLists.txt
M libc/src/__support/CPP/simd.h
M libc/src/__support/fixed_point/CMakeLists.txt
M libc/src/__support/fixed_point/fx_bits.h
M libc/src/__support/fixed_point/fx_rep.h
M libc/src/__support/freelist.cpp
M libc/src/__support/freelist_heap.h
M libc/src/__support/mathvec/CMakeLists.txt
A libc/src/__support/mathvec/acosf.h
A libc/src/__support/mathvec/acoshf.h
A libc/src/__support/mathvec/acospif.h
A libc/src/__support/mathvec/asinf.h
A libc/src/__support/mathvec/asinhf.h
A libc/src/__support/mathvec/asinpif.h
A libc/src/__support/mathvec/atanf.h
A libc/src/__support/mathvec/atanhf.h
A libc/src/__support/mathvec/cbrtf.h
M libc/src/__support/mathvec/common_constants.h
A libc/src/__support/mathvec/cosf.h
A libc/src/__support/mathvec/coshf.h
A libc/src/__support/mathvec/cospif.h
A libc/src/__support/mathvec/erff.h
A libc/src/__support/mathvec/exp10f.h
A libc/src/__support/mathvec/exp10m1f.h
A libc/src/__support/mathvec/exp2f.h
A libc/src/__support/mathvec/exp2m1f.h
M libc/src/__support/mathvec/expf.h
M libc/src/__support/mathvec/expf_utils.h
A libc/src/__support/mathvec/expm1f.h
A libc/src/__support/mathvec/log10f.h
A libc/src/__support/mathvec/log1pf.h
A libc/src/__support/mathvec/log2f.h
A libc/src/__support/mathvec/logf.h
A libc/src/__support/mathvec/rsqrtf.h
A libc/src/__support/mathvec/sinf.h
A libc/src/__support/mathvec/sinhf.h
A libc/src/__support/mathvec/sinpif.h
A libc/src/__support/mathvec/sqrtf.h
A libc/src/__support/mathvec/tanf.h
A libc/src/__support/mathvec/tanhf.h
A libc/src/__support/mathvec/tanpif.h
M libc/src/mathvec/CMakeLists.txt
A libc/src/mathvec/abi_prefix.h
A libc/src/mathvec/acosf.h
A libc/src/mathvec/acoshf.h
A libc/src/mathvec/acospif.h
A libc/src/mathvec/asinf.h
A libc/src/mathvec/asinhf.h
A libc/src/mathvec/asinpif.h
A libc/src/mathvec/atanf.h
A libc/src/mathvec/atanhf.h
A libc/src/mathvec/cbrtf.h
A libc/src/mathvec/cosf.h
A libc/src/mathvec/coshf.h
A libc/src/mathvec/cospif.h
A libc/src/mathvec/erff.h
A libc/src/mathvec/exp10f.h
A libc/src/mathvec/exp10m1f.h
A libc/src/mathvec/exp2f.h
A libc/src/mathvec/exp2m1f.h
M libc/src/mathvec/expf.h
A libc/src/mathvec/expm1f.h
M libc/src/mathvec/generic/CMakeLists.txt
A libc/src/mathvec/generic/acosf.cpp
A libc/src/mathvec/generic/acoshf.cpp
A libc/src/mathvec/generic/acospif.cpp
A libc/src/mathvec/generic/asinf.cpp
A libc/src/mathvec/generic/asinhf.cpp
A libc/src/mathvec/generic/asinpif.cpp
A libc/src/mathvec/generic/atanf.cpp
A libc/src/mathvec/generic/atanhf.cpp
A libc/src/mathvec/generic/cbrtf.cpp
A libc/src/mathvec/generic/cosf.cpp
A libc/src/mathvec/generic/coshf.cpp
A libc/src/mathvec/generic/cospif.cpp
A libc/src/mathvec/generic/erff.cpp
A libc/src/mathvec/generic/exp10f.cpp
A libc/src/mathvec/generic/exp10m1f.cpp
A libc/src/mathvec/generic/exp2f.cpp
A libc/src/mathvec/generic/exp2m1f.cpp
M libc/src/mathvec/generic/expf.cpp
A libc/src/mathvec/generic/expm1f.cpp
A libc/src/mathvec/generic/log10f.cpp
A libc/src/mathvec/generic/log1pf.cpp
A libc/src/mathvec/generic/log2f.cpp
A libc/src/mathvec/generic/logf.cpp
A libc/src/mathvec/generic/rsqrtf.cpp
A libc/src/mathvec/generic/sinf.cpp
A libc/src/mathvec/generic/sinhf.cpp
A libc/src/mathvec/generic/sinpif.cpp
A libc/src/mathvec/generic/sqrtf.cpp
A libc/src/mathvec/generic/tanf.cpp
A libc/src/mathvec/generic/tanhf.cpp
A libc/src/mathvec/generic/tanpif.cpp
A libc/src/mathvec/log10f.h
A libc/src/mathvec/log1pf.h
A libc/src/mathvec/log2f.h
A libc/src/mathvec/logf.h
A libc/src/mathvec/rsqrtf.h
A libc/src/mathvec/sinf.h
A libc/src/mathvec/sinhf.h
A libc/src/mathvec/sinpif.h
A libc/src/mathvec/sqrtf.h
A libc/src/mathvec/tanf.h
A libc/src/mathvec/tanhf.h
A libc/src/mathvec/tanpif.h
M libc/src/stdfix/CMakeLists.txt
A libc/src/stdfix/divik.cpp
A libc/src/stdfix/divik.h
A libc/src/stdfix/divilk.cpp
A libc/src/stdfix/divilk.h
A libc/src/stdfix/divilr.cpp
A libc/src/stdfix/divilr.h
A libc/src/stdfix/divir.cpp
A libc/src/stdfix/divir.h
A libc/src/stdfix/diviuk.cpp
A libc/src/stdfix/diviuk.h
A libc/src/stdfix/diviulk.cpp
A libc/src/stdfix/diviulk.h
A libc/src/stdfix/diviulr.cpp
A libc/src/stdfix/diviulr.h
A libc/src/stdfix/diviur.cpp
A libc/src/stdfix/diviur.h
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/baremetal/CMakeLists.txt
A libc/src/stdlib/baremetal/malloc_usable_size.cpp
A libc/src/stdlib/malloc_usable_size.h
M libc/src/sys/select/linux/CMakeLists.txt
M libc/src/sys/select/linux/select.cpp
M libc/src/sys/select/select.h
M libc/src/sys/utsname/linux/CMakeLists.txt
M libc/src/sys/utsname/linux/uname.cpp
M libc/src/sys/utsname/uname.h
M libc/src/sys/wait/linux/CMakeLists.txt
M libc/src/sys/wait/wait4.h
M libc/src/sys/wait/wait4Impl.h
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/gethostname.cpp
M libc/test/include/netinet_in_test.cpp
M libc/test/src/__support/freelist_heap_test.cpp
M libc/test/src/mathvec/CMakeLists.txt
A libc/test/src/mathvec/UnitTestWrappers.h
A libc/test/src/mathvec/acosf_test.cpp
A libc/test/src/mathvec/acoshf_test.cpp
A libc/test/src/mathvec/acospif_test.cpp
A libc/test/src/mathvec/asinf_test.cpp
A libc/test/src/mathvec/asinhf_test.cpp
A libc/test/src/mathvec/asinpif_test.cpp
A libc/test/src/mathvec/atanf_test.cpp
A libc/test/src/mathvec/atanhf_test.cpp
A libc/test/src/mathvec/cbrtf_test.cpp
A libc/test/src/mathvec/cosf_test.cpp
A libc/test/src/mathvec/coshf_test.cpp
A libc/test/src/mathvec/cospif_test.cpp
A libc/test/src/mathvec/erff_test.cpp
M libc/test/src/mathvec/exhaustive/CMakeLists.txt
A libc/test/src/mathvec/exhaustive/acosf_test.cpp
A libc/test/src/mathvec/exhaustive/acoshf_test.cpp
A libc/test/src/mathvec/exhaustive/acospif_test.cpp
A libc/test/src/mathvec/exhaustive/asinf_test.cpp
A libc/test/src/mathvec/exhaustive/asinhf_test.cpp
A libc/test/src/mathvec/exhaustive/asinpif_test.cpp
A libc/test/src/mathvec/exhaustive/atanf_test.cpp
A libc/test/src/mathvec/exhaustive/atanhf_test.cpp
A libc/test/src/mathvec/exhaustive/cbrtf_test.cpp
A libc/test/src/mathvec/exhaustive/cosf_test.cpp
A libc/test/src/mathvec/exhaustive/coshf_test.cpp
A libc/test/src/mathvec/exhaustive/cospif_test.cpp
A libc/test/src/mathvec/exhaustive/erff_test.cpp
M libc/test/src/mathvec/exhaustive/exhaustive_test.h
A libc/test/src/mathvec/exhaustive/exp10f_test.cpp
A libc/test/src/mathvec/exhaustive/exp10m1f_test.cpp
A libc/test/src/mathvec/exhaustive/exp2f_test.cpp
A libc/test/src/mathvec/exhaustive/exp2m1f_test.cpp
M libc/test/src/mathvec/exhaustive/expf_test.cpp
A libc/test/src/mathvec/exhaustive/expm1f_test.cpp
A libc/test/src/mathvec/exhaustive/log10f_test.cpp
A libc/test/src/mathvec/exhaustive/log1pf_test.cpp
A libc/test/src/mathvec/exhaustive/log2f_test.cpp
A libc/test/src/mathvec/exhaustive/logf_test.cpp
A libc/test/src/mathvec/exhaustive/rsqrtf_test.cpp
A libc/test/src/mathvec/exhaustive/sinf_test.cpp
A libc/test/src/mathvec/exhaustive/sinhf_test.cpp
A libc/test/src/mathvec/exhaustive/sinpif_test.cpp
A libc/test/src/mathvec/exhaustive/sqrtf_test.cpp
A libc/test/src/mathvec/exhaustive/tanf_test.cpp
A libc/test/src/mathvec/exhaustive/tanhf_test.cpp
A libc/test/src/mathvec/exhaustive/tanpif_test.cpp
A libc/test/src/mathvec/exp10f_test.cpp
A libc/test/src/mathvec/exp10m1f_test.cpp
A libc/test/src/mathvec/exp2f_test.cpp
A libc/test/src/mathvec/exp2m1f_test.cpp
M libc/test/src/mathvec/expf_test.cpp
A libc/test/src/mathvec/expm1f_test.cpp
A libc/test/src/mathvec/log10f_test.cpp
A libc/test/src/mathvec/log1pf_test.cpp
A libc/test/src/mathvec/log2f_test.cpp
A libc/test/src/mathvec/logf_test.cpp
A libc/test/src/mathvec/rsqrtf_test.cpp
A libc/test/src/mathvec/sinf_test.cpp
A libc/test/src/mathvec/sinhf_test.cpp
A libc/test/src/mathvec/sinpif_test.cpp
A libc/test/src/mathvec/sqrtf_test.cpp
A libc/test/src/mathvec/tanf_test.cpp
A libc/test/src/mathvec/tanhf_test.cpp
A libc/test/src/mathvec/tanpif_test.cpp
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/DiviFxTest.h
A libc/test/src/stdfix/divik_test.cpp
A libc/test/src/stdfix/divilk_test.cpp
A libc/test/src/stdfix/divilr_test.cpp
A libc/test/src/stdfix/divir_test.cpp
A libc/test/src/stdfix/diviuk_test.cpp
A libc/test/src/stdfix/diviulk_test.cpp
A libc/test/src/stdfix/diviulr_test.cpp
A libc/test/src/stdfix/diviur_test.cpp
M libcxx/cmake/caches/Generic-llvm-libc.cmake
M libcxx/include/__algorithm/copy_n.h
M libcxx/include/__algorithm/for_each_n.h
M libcxx/include/__algorithm/generate_n.h
M libcxx/include/__algorithm/ranges_for_each_n.h
M libcxx/include/__bit_reference
M libcxx/src/include/overridable_function.h
M libcxx/src/new.cpp
A libcxx/test/benchmarks/algorithms/modifying/replace_copy.bench.cpp
A libcxx/test/benchmarks/algorithms/sorting/binary_search.bench.cpp
A libcxx/test/benchmarks/algorithms/sorting/equal_range.bench.cpp
M libcxx/test/benchmarks/algorithms/sorting/lower_upper_bound.bench.cpp
M libcxx/test/configs/llvm-libc++-llvm-libc.cfg.in
A libcxx/test/libcxx/algorithms/alg.nonmodifying/alg.foreach/assert.for_each_n.pass.cpp
A libcxx/test/libcxx/algorithms/alg.nonmodifying/alg.foreach/assert.ranges.for_each_n.pass.cpp
M libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
M libcxx/test/libcxx/language.support/support.dynamic/assert.nothrow_new_not_overridden_fno_exceptions.pass.cpp
M libcxx/test/libcxx/language.support/support.dynamic/new_dont_return_nullptr.pass.cpp
M libcxx/test/libcxx/thread/thread.condition/PR30202_notify_from_pthread_created_thread.pass.cpp
M libcxx/test/libcxx/thread/thread.threads/thread.thread.class/thread.thread.member/native_handle.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.generate/generate_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.generate/ranges_generate_n.pass.cpp
M libcxx/test/std/depr/depr.c.headers/wchar_h.compile.pass.cpp
M libcxx/test/std/depr/depr.c.headers/wctype_h.compile.pass.cpp
M libcxx/test/std/input.output/syncstream/osyncstream/thread/several_threads.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.member.ops/divide_equal_complex.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.ops/complex_divide_complex.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.ops/scalar_divide_complex.pass.cpp
M libcxx/test/std/numerics/rand/rand.dist/rand.dist.bern/rand.dist.bern.bin/eval.PR44847.pass.cpp
M libcxx/test/std/numerics/rand/rand.dist/rand.dist.bern/rand.dist.bern.bin/io.pass.cpp
M libcxx/test/std/strings/c.strings/cwchar.pass.cpp
M libcxx/test/std/strings/c.strings/cwctype.pass.cpp
M libcxx/test/std/strings/string.conversions/to_wstring.pass.cpp
M libcxx/test/std/thread/thread.condition/notify_all_at_thread_exit_lwg3343.pass.cpp
M libcxx/test/std/thread/thread.threads/thread.thread.this/sleep_for.signals.pass.cpp
M libcxx/test/std/time/time.hash/time.hash_enabled.pass.cpp
M libcxxabi/src/stdlib_new_delete.cpp
M libcxxabi/test/configs/llvm-libc++abi-llvm-libc.cfg.in
M libsycl/test/basic/parallel_for_indexers.cpp
M libsycl/unittests/mock/helpers.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
M lld/test/ELF/local-symbols-order.s
M lld/test/ELF/lto/parallel-internalize.ll
M lld/test/ELF/ppc64-local-entry.s
M lld/test/ELF/relocatable-comdat-multiple.s
M lld/test/ELF/relocatable-comdat2.s
M lld/test/ELF/relocatable-discard-locals.s
M lld/test/ELF/relocatable-gc.s
M lld/test/ELF/relocatable.s
M lld/test/ELF/strtab-nodedup.s
M lldb/cmake/modules/FindPythonAndSwig.cmake
M lldb/examples/python/templates/operating_system.py
M lldb/examples/python/templates/scripted_breakpoint.py
M lldb/examples/python/templates/scripted_frame_provider.py
M lldb/examples/python/templates/scripted_hook.py
M lldb/examples/python/templates/scripted_platform.py
M lldb/examples/python/templates/scripted_process.py
M lldb/examples/python/templates/scripted_thread_plan.py
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h
M lldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp
M lldb/source/Plugins/ObjectFile/ELF/ELFHeader.cpp
M lldb/source/Plugins/ObjectFile/ELF/ELFHeader.h
M lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.cpp
M lldb/test/API/driver/longpath/TestLongPathDriver.py
M lldb/test/API/functionalities/longpath/TestLongPath.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_breakpointLocations.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setBreakpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setExceptionBreakpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setFunctionBreakpoints.py
M lldb/test/API/tools/lldb-dap/io/TestDAP_io.py
M lldb/test/API/tools/lldb-dap/launch/io/DAP_launch_io.py
M lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_integratedTerminal.py
M lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_internalConsole.py
M lldb/test/API/tools/lldb-dap/launch/io/main.cpp
M lldb/test/API/tools/lldb-dap/longpath/TestDAP_launch_longPath.py
M lldb/test/Shell/helper/toolchain.py
M lldb/test/Shell/lit.cfg.py
M llvm/cmake/modules/LLVMExternalProjectUtils.cmake
M llvm/docs/LFI.rst
M llvm/docs/LangRef.md
M llvm/include/llvm-c/Orc.h
M llvm/include/llvm/ADT/BitVector.h
M llvm/include/llvm/ADT/Eytzinger.h
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
M llvm/include/llvm/ADT/GenericUniformityImpl.h
M llvm/include/llvm/ADT/GenericUniformityInfo.h
M llvm/include/llvm/ADT/SmallBitVector.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
M llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/include/llvm/DebugInfo/PDB/Native/LinePrinter.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/FixedMetadataKinds.def
M llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/MC/MCLFIRewriter.h
M llvm/include/llvm/MC/MCObjectFileInfo.h
M llvm/include/llvm/MC/MCSchedule.h
M llvm/include/llvm/ObjectYAML/COFFYAML.h
M llvm/include/llvm/ObjectYAML/yaml2obj.h
M llvm/lib/Analysis/CFG.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/MachineCycleAnalysis.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/lib/CodeGen/TargetSchedule.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Globals.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/LineEditor/LineEditor.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Object/GOFFObjectFile.cpp
M llvm/lib/ObjectYAML/COFFEmitter.cpp
M llvm/lib/ObjectYAML/yaml2obj.cpp
M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/WebAssembly/CMakeLists.txt
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyAddMissingPrototypes.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyArgumentMove.cpp
A llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
A llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyNullifyDebugValueLists.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyOptimizeReturned.cpp
A llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyReduceToAnyAllTrue.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRefTypeMem2Local.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
M llvm/lib/Target/X86/X86CmovConversion.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Utils/AssignGUID.cpp
M llvm/lib/Transforms/Utils/CloneModule.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/AliasSet/memset.ll
M llvm/test/Analysis/CostModel/AMDGPU/sin.ll
M llvm/test/Analysis/KernelInfo/enable-kernel-info/amdgpu.test
M llvm/test/Analysis/KernelInfo/flat-addrspace/amdgpu.test
M llvm/test/Analysis/KernelInfo/launch-bounds/amdgpu.ll
M llvm/test/Analysis/KernelInfo/openmp/README.md
M llvm/test/Analysis/KernelInfo/openmp/amdgpu.ll
M llvm/test/Assembler/atomic.ll
A llvm/test/Assembler/invalid-load-store-atomic-elementwise.ll
A llvm/test/Bitcode/atomic-load-store-elementwise.ll
M llvm/test/Bitcode/compatibility.ll
A llvm/test/CodeGen/AArch64/GlobalISel/combine-fdiv-inlineasm-operand.mir
M llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-bf16.ll
R llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-fp-trunc-bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-returnaddress.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sopc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-packed.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/known-bits-sbfe.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/known-fpclass-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-splat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctls.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant32bit.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-legalize-range-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer-wrong-insert-point.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-cse-nonlocal-convergent-instrs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-legalize-atomic.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-buildvector-identities.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-merge.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-trunc-bitcast-buildvector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-unmerge-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-load-and-mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-fptrunc_fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-redundant-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-sext_inreg-to-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-shuffle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-merge-values-build-vector-s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shader-epilogs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-divergent-addr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-uniform-addr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
M llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll
M llvm/test/CodeGen/AMDGPU/add_i128.ll
M llvm/test/CodeGen/AMDGPU/add_i64.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/alignbit-pat.ll
M llvm/test/CodeGen/AMDGPU/allow-check.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-flat-scratch-init-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-intrinsic-missing-nocallback.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-nocallback-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-trap-leaf.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-log.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-llvm-debuginfo-analyzer.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-uniform-waterfall.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-uniform-intrinsic-combine.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-uniform-temporal-divergence.ll
M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll
M llvm/test/CodeGen/AMDGPU/atomic-optimizer-promote-i8.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimization_split_dt_update.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
M llvm/test/CodeGen/AMDGPU/attributor-wwm.ll
M llvm/test/CodeGen/AMDGPU/barrier-elimination.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-uniformity.ll
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-encoding.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
M llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
M llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
M llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/commute_modifiers.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
M llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
M llvm/test/CodeGen/AMDGPU/convergent.mir
M llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
M llvm/test/CodeGen/AMDGPU/cttz-elts.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
M llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll
M llvm/test/CodeGen/AMDGPU/debug-independence-revertScheduling.ll
M llvm/test/CodeGen/AMDGPU/debug-independence-scheduleRegion.ll
M llvm/test/CodeGen/AMDGPU/debug-value.ll
M llvm/test/CodeGen/AMDGPU/debug-value2.ll
M llvm/test/CodeGen/AMDGPU/debug_frame.ll
M llvm/test/CodeGen/AMDGPU/default_amdhsa_code_object_version.ll
M llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir
M llvm/test/CodeGen/AMDGPU/disable-preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/do-not-unify-divergent-exit-nodes-with-musttail.ll
M llvm/test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll
M llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll
M llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
M llvm/test/CodeGen/AMDGPU/extload-align.ll
M llvm/test/CodeGen/AMDGPU/extract-load-i1.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
M llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
M llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
M llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
M llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll
M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
M llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir
M llvm/test/CodeGen/AMDGPU/fold-over-exec.mir
M llvm/test/CodeGen/AMDGPU/fold-readlane.mir
M llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll
M llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll
M llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
M llvm/test/CodeGen/AMDGPU/freeze-other-uses-issue-198094.ll
M llvm/test/CodeGen/AMDGPU/generic-targets-require-v6.ll
M llvm/test/CodeGen/AMDGPU/global-alias.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/hoist-cond.ll
M llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-deduced-arg-attr.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll
M llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir
M llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll
M llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-attributes.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/inline-calls.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-sgmask.ll
M llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll
M llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
M llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
M llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
M llvm/test/CodeGen/AMDGPU/issue120256-annotate-constexpr-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/issue176578.ll
M llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
M llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll
M llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll
M llvm/test/CodeGen/AMDGPU/lds-alignment.ll
M llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
M llvm/test/CodeGen/AMDGPU/lds-size.ll
M llvm/test/CodeGen/AMDGPU/liveness.mir
M llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.2dmsaa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-vector-sink.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-barriers.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-cluster-barrier.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-split-barriers.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-check-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
M llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
M llvm/test/CodeGen/AMDGPU/madmk-madak-encoding-size.ll
M llvm/test/CodeGen/AMDGPU/madmk.ll
M llvm/test/CodeGen/AMDGPU/max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir
M llvm/test/CodeGen/AMDGPU/mem-builtins.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-m0.mir
M llvm/test/CodeGen/AMDGPU/mesa_regression.ll
M llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
M llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir
M llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
M llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
M llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
M llvm/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll
M llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/nullptr.ll
M llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
M llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
M llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-bf16.ll
M llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll
M llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir
M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll
M llvm/test/CodeGen/AMDGPU/pr155452.ll
M llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll
M llvm/test/CodeGen/AMDGPU/printf_builtin.ll
M llvm/test/CodeGen/AMDGPU/printf_nobuiltin.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-budget-exhausted.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-shufflevector.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/propagate-amdgpu-cluster-dims.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/rcp_iflag.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll
M llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir
M llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/reduction.ll
M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
M llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
M llvm/test/CodeGen/AMDGPU/register-count-comments.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir
M llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
M llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-phi.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll
M llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdivrem24.ll
M llvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select-opt.ll
M llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
M llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/setcc-select.ll
M llvm/test/CodeGen/AMDGPU/setcc-sext.ll
M llvm/test/CodeGen/AMDGPU/setcc.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir
M llvm/test/CodeGen/AMDGPU/sgprcopies.ll
M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/si-i1-copies.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
M llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll
M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
M llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
M llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
M llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
M llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
M llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir
M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
M llvm/test/CodeGen/AMDGPU/subreg_interference.mir
M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
M llvm/test/CodeGen/AMDGPU/udivrem64.r600.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
M llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
M llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
M llvm/test/CodeGen/AMDGPU/verify-sop.mir
M llvm/test/CodeGen/AMDGPU/vgpr-count-compute.ll
M llvm/test/CodeGen/AMDGPU/vgpr-count-graphics-chain.ll
M llvm/test/CodeGen/AMDGPU/vgpr-count-graphics.ll
M llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
A llvm/test/CodeGen/AMDGPU/vgpr-setreg-pred-block.mir
M llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
M llvm/test/CodeGen/AMDGPU/vni8-live-reg-opt.ll
M llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-debug-non-first-terminators.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir
M llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll
M llvm/test/CodeGen/AMDGPU/zext-lid.ll
M llvm/test/CodeGen/BPF/sink-min-max.ll
M llvm/test/CodeGen/MIR/AMDGPU/cfi-pseudos.mir
M llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
M llvm/test/CodeGen/MIR/AMDGPU/dead-flag-on-use-operand-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/instr-mmra-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/instr-mmra.mir
M llvm/test/CodeGen/MIR/AMDGPU/killed-flag-on-def-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-min-num-agprs.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-expect-id.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-parse.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-undefine-matadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-cfi-unsigned-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-name-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-mfi.ll
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-stack-type-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/ptradd-flags.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu-errors.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_loadcnt_dscnt-errors.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_loadcnt_dscnt.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt-errors.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt_soft.mir
M llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtreg-uses-unallocatable-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-split.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
A llvm/test/CodeGen/Mips/fake-use.ll
M llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
A llvm/test/CodeGen/RISCV/sched-model-load-latency.ll
A llvm/test/CodeGen/RISCV/sched-model-mispredict-penalty.ll
A llvm/test/CodeGen/RISCV/short-forward-branch-opt-zibi.ll
A llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll
M llvm/test/CodeGen/WebAssembly/add-prototypes.ll
M llvm/test/CodeGen/WebAssembly/lower-em-exceptions-allowed.ll
M llvm/test/CodeGen/X86/bitcnt-load-with-cmov.ll
M llvm/test/CodeGen/X86/bmi.ll
M llvm/test/CodeGen/X86/bmi2.ll
M llvm/test/CodeGen/X86/fmaddsub-combine.ll
M llvm/test/CodeGen/X86/fmsubadd-combine.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
M llvm/test/CodeGen/X86/vpdpwssd.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
M llvm/test/DebugInfo/AMDGPU/bitcast-store-combine-debugloc.ll
M llvm/test/DebugInfo/AMDGPU/cfi.ll
M llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll
M llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll
M llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll
M llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll
M llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-cfi-directives.s
M llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll
M llvm/test/DebugInfo/AMDGPU/print-reg-name.s
M llvm/test/DebugInfo/AMDGPU/variable-locations.ll
M llvm/test/DebugInfo/AMDGPU/wqm-wwm-debug-loc.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512dq-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll
M llvm/test/MC/AArch64/LFI/guard-elim.s
M llvm/test/MC/AArch64/LFI/mem-lr.s
A llvm/test/MC/AArch64/LFI/pac-errors.s
A llvm/test/MC/AArch64/LFI/pac.s
M llvm/test/MC/AArch64/LFI/return.s
M llvm/test/MC/AMDGPU/gfx13_asm_vds.s
A llvm/test/TableGen/CodeEmitterBaseEncodingPool.td
M llvm/test/TableGen/HwModeEncodeAPInt.td
M llvm/test/TableGen/MacroFusion.td
M llvm/test/Transforms/AggressiveInstCombine/AMDGPU/fold-consecutive-loads.ll
M llvm/test/Transforms/AggressiveInstCombine/AMDGPU/fold-loads-multiple-uses.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i64-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i64-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-mmra.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-private-gas.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-flat-noalias-addrspace.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-fp-vector.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-integer-ops-0-to-add-0.ll
M llvm/test/Transforms/ConstraintElimination/induction-nowrap-from-scev-not-ir.ll
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-wrapping.ll
M llvm/test/Transforms/ConstraintElimination/or-non-negative.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/phinode-address-infer.ll
M llvm/test/Transforms/InstCombine/AMDGPU/bitcast-fold-lane-ops.ll
M llvm/test/Transforms/InstCombine/AMDGPU/fmed3.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wave.shuffle.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wavefrontsize.ll
M llvm/test/Transforms/InstCombine/AMDGPU/mbcnt.ll
M llvm/test/Transforms/InstCombine/AMDGPU/rcp-contract-rsq.ll
M llvm/test/Transforms/InstCombine/AMDGPU/simplify-demanded-vector-elts-lane-intrinsics.ll
M llvm/test/Transforms/InstCombine/AMDGPU/trivially-uniform.ll
M llvm/test/Transforms/InstCombine/mul.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/load-i1-misaligned.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-addressing-mode-loops.ll
A llvm/test/Transforms/LoopUnroll/full-unroll-scev-invalidation.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/buffer-fat-pointer.ll
M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i8-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/handle-iptr-with-data-layout-to-not-assert.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-01uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i32-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i64-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll
A llvm/test/Transforms/LowerTypeTests/icall-branch-funnel-invalid-operand.ll
M llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/exp2-vectorize.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/external-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/extract-ordering.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/inst-count-heuristic.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/vectorize-i8.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/zext-duplicate-shift.ll
A llvm/test/Transforms/SLPVectorizer/X86/loop-invariant-gather-inst-count.ll
M llvm/test/Transforms/SandboxVectorizer/AMDGPU/basic.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/amdgpu-large-lds-offset.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/rebuild-trunc.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reunite-exts-source-types.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reunite-exts.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/combine-scalar-selects.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-i8.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/shuffles-of-length-changing-shuffles.ll
M llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
M llvm/test/tools/llvm-reduce/mir/drop-ir-references.mir
M llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
M llvm/test/tools/llvm-reduce/mir/infer-triple.mir
M llvm/test/tools/llvm-reduce/mir/input-file-does-not-exist.mir
M llvm/test/tools/llvm-reduce/mir/instr-reduce-dead-def.mir
M llvm/test/tools/llvm-reduce/mir/multiple-functions.mir
M llvm/test/tools/llvm-reduce/mir/preserve-block-info.mir
M llvm/test/tools/llvm-reduce/mir/preserve-frame-info.mir
M llvm/test/tools/llvm-reduce/mir/preserve-func-info.mir
M llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir
M llvm/test/tools/llvm-reduce/mir/preserve-max-call-frame-size.mir
M llvm/test/tools/llvm-reduce/mir/preserve-mem-operands.mir
M llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
M llvm/test/tools/llvm-reduce/mir/reduce-instruction-flags.mir
M llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-defs.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-hints.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-masks.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-uses.mir
M llvm/test/tools/llvm-reduce/mir/remove-frame-destroy.mir
M llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
M llvm/test/tools/llvm-reduce/mir/subreg-def1.mir
M llvm/test/tools/llvm-reduce/mir/tracks-reg-liveness.mir
M llvm/test/tools/llvm-reduce/mir/undef-virt-reg.mir
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize-with-call.ll
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize.ll
M llvm/test/tools/llvm-split/AMDGPU/declarations.ll
M llvm/test/tools/llvm-split/AMDGPU/indirect-call-inline-asm-debug.ll
M llvm/test/tools/llvm-split/AMDGPU/indirect-call-inline-asm.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-cost-ranking.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-duplication.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-external.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-indirect-callee-md.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-indirect.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-overridable.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables-noexternal.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-load-balancing.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-no-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging-weak_odr.ll
M llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging.ll
M llvm/test/tools/llvm-split/AMDGPU/non-kernels-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/non-kernels-dependency-indirect.ll
M llvm/test/tools/llvm-split/AMDGPU/preserve-globals.ll
M llvm/test/tools/llvm-split/AMDGPU/recursive-search-2.ll
M llvm/test/tools/llvm-split/AMDGPU/recursive-search-8.ll
A llvm/test/tools/yaml2obj/COFF/output-limit.yaml
M llvm/tools/yaml2obj/yaml2obj.cpp
M llvm/unittests/ADT/BitVectorTest.cpp
M llvm/unittests/ADT/EytzingerTest.cpp
M llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
M llvm/unittests/IR/VerifierTest.cpp
M llvm/unittests/Target/AMDGPU/GCNRegPressureTest.cpp
M llvm/utils/TableGen/CodeEmitterGen.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.h
M llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
M llvm/utils/TableGen/RegisterBankEmitter.cpp
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
M llvm/utils/profcheck-xfail.txt
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
A mlir/include/mlir/Conversion/SCFToAffine/SCFToAffine.h
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGAttributes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Conversion/CMakeLists.txt
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
A mlir/lib/Conversion/SCFToAffine/CMakeLists.txt
A mlir/lib/Conversion/SCFToAffine/SCFToAffine.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
A mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm-mma-fp8.mlir
A mlir/test/Conversion/SCFToAffine/scf-to-affine.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Dialect/MemRef/elide-reinterpret-cast.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-barrier-gang-private-init.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-block-redundant.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-launch-mapping.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-predicate-region-reuse-barrier.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-predicate-region.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-private-local-gang-redundant.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-privatize-local.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-privatize-routine-seq.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-privatize-threadprivate.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-array-shared.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-array.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-block-combine-no-reload.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-combine-region-private-dest.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reuse-barrier-sibling-region-privatize.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-routine-call-nested-if.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-routine-worker-call-with-thread-y-reduction.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-private-dynamic-nw.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-vector-reuse-barrier.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-vector-subgroup-align.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
M mlir/test/Target/Cpp/common-cpp.mlir
A mlir/test/Target/LLVMIR/openmp-taskwait-depend.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M offload/liboffload/API/Program.td
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.h
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.h
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/level_zero/include/L0Kernel.h
M offload/plugins-nextgen/level_zero/include/L0Options.h
M offload/plugins-nextgen/level_zero/include/L0Trace.h
M offload/plugins-nextgen/level_zero/src/L0Options.cpp
M offload/plugins-nextgen/level_zero/src/L0Program.cpp
M offload/plugins-nextgen/level_zero/src/L0Queue.cpp
M offload/test/lit.cfg
M offload/unittests/OffloadAPI/common/Environment.cpp
M offload/unittests/OffloadAPI/common/Environment.hpp
M offload/unittests/OffloadAPI/program/olCreateProgram.cpp
M openmp/runtime/src/kmp_barrier.cpp
M orc-rt/include/orc-rt-c/WrapperFunction.h
M orc-rt/include/orc-rt/InProcessControllerAccess.h
M orc-rt/include/orc-rt/Session.h
M orc-rt/lib/executor/InProcessControllerAccess.cpp
M orc-rt/lib/executor/StandaloneMachOUnwindInfoRegistrar.cpp
M orc-rt/lib/executor/Unix/NativeDylibAPIs.inc
M orc-rt/lib/executor/Unix/NativeMemoryAPIs.inc
M orc-rt/lib/executor/sps-ci/MemoryAccessSPSCI.cpp
M orc-rt/test/unit/AllocActionTest.cpp
M orc-rt/test/unit/CompilerTest.cpp
M orc-rt/test/unit/ErrorCAPITest.cpp
M orc-rt/test/unit/ErrorExceptionInteropTest.cpp
M orc-rt/test/unit/ErrorTest.cpp
M orc-rt/test/unit/LockedAccessTest.cpp
M orc-rt/test/unit/QueueingRunnerTest.cpp
M orc-rt/test/unit/RTTITest.cpp
M orc-rt/test/unit/SPSWrapperFunctionTest.cpp
M orc-rt/test/unit/SessionTest.cpp
M orc-rt/test/unit/ThreadPoolRunnerTest.cpp
M orc-rt/test/unit/WrapperFunctionBufferTest.cpp
M polly/lib/CodeGen/BlockGenerators.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
M polly/lib/Transform/DeLICM.cpp
A polly/test/CodeGen/issue205732.ll
A polly/test/DeLICM/outofquota-greedycollapse.ll
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/string/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/mman/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/resource/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/unistd/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
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-----------
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Compare: https://github.com/llvm/llvm-project/compare/4079a9815e50...beee8c8708c1
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