[all-commits] [llvm/llvm-project] 2746fc: AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Wed Jul 15 05:47:49 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2746fc6981516c9e26dbdaa7ba254279d391b534
      https://github.com/llvm/llvm-project/commit/2746fc6981516c9e26dbdaa7ba254279d391b534
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-splat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctls.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-divrem.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp-s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir

  Log Message:
  -----------
  AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (43) (#209733)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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