[all-commits] [llvm/llvm-project] 8dd737: [RISCV][P-ext] Support 4i16/v8i8 MULHS/MULHU/MULHS...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8dd73767aa9081cf67cd6aaa1358970034a7d697
      https://github.com/llvm/llvm-project/commit/8dd73767aa9081cf67cd6aaa1358970034a7d697
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-06-05 (Fri, 05 Jun 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvp-simd-64.ll

  Log Message:
  -----------
  [RISCV][P-ext] Support 4i16/v8i8 MULHS/MULHU/MULHSU for division by constant (#201747)

Update the mulhs+add->mulhsu combine to create a split mulhsu for 64-bit
types. LegalizeVectorOps will ignore target specific opcodes so we can't
custom lower it later.



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