[all-commits] [llvm/llvm-project] 9f175c: [RISCV] fix SP recovery in the function epilogue

dlav-sc via All-commits all-commits at lists.llvm.org
Wed Oct 2 04:29:44 PDT 2024


  Branch: refs/heads/users/dlav-sc/riscv-sp-recovery
  Home:   https://github.com/llvm/llvm-project
  Commit: 9f175cd6591c380f31b02343e3fea0e430ff6ca8
      https://github.com/llvm/llvm-project/commit/9f175cd6591c380f31b02343e3fea0e430ff6ca8
  Author: Daniil Avdeev <daniil.avdeev at syntacore.com>
  Date:   2024-10-02 (Wed, 02 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/lib/Target/RISCV/RISCVFrameLowering.h

  Log Message:
  -----------
  [RISCV] fix SP recovery in the function epilogue

This patch fixes SP register recovery in the function epilogue.


  Commit: 1ec6df87bdd005554c77b551d420ac65b64aa7a8
      https://github.com/llvm/llvm-project/commit/1ec6df87bdd005554c77b551d420ac65b64aa7a8
  Author: Daniil Avdeev <daniil.avdeev at syntacore.com>
  Date:   2024-10-02 (Wed, 02 Oct 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/branch-relaxation.ll
    M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
    M llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
    M llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
    M llvm/test/CodeGen/RISCV/stack-realignment.ll

  Log Message:
  -----------
  [RISCV] update tests


Compare: https://github.com/llvm/llvm-project/compare/1748ccf3b892...1ec6df87bdd0

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