[all-commits] [llvm/llvm-project] 41f1b4: [RISCV] Account for zvfhmin and zvfbfmin promotion...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 41f1b467a29d2ca4e35df37c3aa79a0a8c04bc4f
      https://github.com/llvm/llvm-project/commit/41f1b467a29d2ca4e35df37c3aa79a0a8c04bc4f
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-09-17 (Tue, 17 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    A llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
    A llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll

  Log Message:
  -----------
  [RISCV] Account for zvfhmin and zvfbfmin promotion in register usage (#108370)

A half with only zvfhmin or bfloat will end up getting promoted to a f32
for most instructions.

Unless the loop consists only of memory ops and permutation instructions
which don't need promoted (is this common?), we'll end up using double
the LMUL than what's currently being returned by getRegUsageForType.

Since this is used by the loop vectorizer, it seems better to be
conservative and assume that any usage of a zvfhmin half/bfloat will end
up being widened to a f32



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications