[all-commits] [llvm/llvm-project] 30d7dc: [RISCV] Add asserts requirement to loop vectorizer...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 30d7dcc1db476b828d3b0a7b5c9bcfbe5bd5f216
      https://github.com/llvm/llvm-project/commit/30d7dcc1db476b828d3b0a7b5c9bcfbe5bd5f216
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-09-17 (Tue, 17 Sep 2024)

  Changed paths:
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll

  Log Message:
  -----------
  [RISCV] Add asserts requirement to loop vectorizer tests

Hopefully this fixes a buildbot failure on fuchsia where opt doesn't
have -debug-only



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