[all-commits] [llvm/llvm-project] c7902d: [InstCombine] Add test for isKnownNonZero() undef ...

[Pengcheng Wang via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/riscv-dont-use-v0-directly-in-patterns
  Home:   https://github.com/llvm/llvm-project
  Commit: c7902d87a5a050b816edfe99e7e093ae63f4e564
      https://github.com/llvm/llvm-project/commit/c7902d87a5a050b816edfe99e7e093ae63f4e564
  Author: Nikita Popov <npopov at redhat.com>
  Date:   2024-04-15 (Mon, 15 Apr 2024)

  Changed paths:
    M llvm/test/Transforms/InstCombine/add.ll

  Log Message:
  -----------
  [InstCombine] Add test for isKnownNonZero() undef miscompile (NFC)


  Commit: 52a1998f15ab0e5b9ff7afa8b92cc714463d5dd8
      https://github.com/llvm/llvm-project/commit/52a1998f15ab0e5b9ff7afa8b92cc714463d5dd8
  Author: Nikita Popov <npopov at redhat.com>
  Date:   2024-04-15 (Mon, 15 Apr 2024)

  Changed paths:
    M llvm/lib/Analysis/ValueTracking.cpp
    M llvm/test/Transforms/InstCombine/add.ll
    M llvm/test/Transforms/InstSimplify/vec-cmp.ll

  Log Message:
  -----------
  [ValueTracking] Don't accept undef in isKnownNonZero()

As the undef can be replaced with a zero value, this is not legal
in the general case. We can only allow poison values. This matches
what the other ValueTracking helpers like computeKnownBits() do.


  Commit: 7177dc2ef7f3a50a1d8b892d7bd298f3d52a1aab
      https://github.com/llvm/llvm-project/commit/7177dc2ef7f3a50a1d8b892d7bd298f3d52a1aab
  Author: fengfeng <153487255+fengfeng09 at users.noreply.github.com>
  Date:   2024-04-15 (Mon, 15 Apr 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    A llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll

  Log Message:
  -----------
  [SDAG] Apply or-disjoint in SelectionDAG::isBaseWithConstantOffset (#88493)

Signed-off-by: feng.feng <feng.feng at iluvatar.com>


  Commit: 6b80e2fef5b0e99f81d1f4a7322b110f9ead3521
      https://github.com/llvm/llvm-project/commit/6b80e2fef5b0e99f81d1f4a7322b110f9ead3521
  Author: laichunfeng <laichunfeng at tencent.com>
  Date:   2024-04-15 (Mon, 15 Apr 2024)

  Changed paths:
    M llvm/lib/CodeGen/MachineScheduler.cpp
    M llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/LoongArch/vector-fp-imm.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/bfloat-convert.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

  Log Message:
  -----------
  [mi-sched] Suppress register pressure with i64. (#88256)

Machine scheduler will suppress register pressure when the scheduling
window is too small, but now it doesn't consider i64 register type,
and this MR extends it into i64 register type, so architecture like
RISCV64 that only supports i64 interger register will have the same
behavior like RISCV32.


  Commit: 2cc0c2104909558680409f8a8f39755936305e72
      https://github.com/llvm/llvm-project/commit/2cc0c2104909558680409f8a8f39755936305e72
  Author: Christian Sigg <csigg at google.com>
  Date:   2024-04-15 (Mon, 15 Apr 2024)

  Changed paths:
    M utils/bazel/llvm-project-overlay/clang/BUILD.bazel

  Log Message:
  -----------
  [clang][bazel] Fix BUILD after f811d7b50957b801788d7b171ddeb25b1fda415a.


  Commit: c9d96c0d77b67c208aaf7f8f2554f972baa412d2
      https://github.com/llvm/llvm-project/commit/c9d96c0d77b67c208aaf7f8f2554f972baa412d2
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-04-15 (Mon, 15 Apr 2024)

  Changed paths:
    M llvm/lib/Analysis/ValueTracking.cpp
    M llvm/lib/CodeGen/MachineScheduler.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    A llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll
    M llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/LoongArch/vector-fp-imm.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/bfloat-convert.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/Transforms/InstCombine/add.ll
    M llvm/test/Transforms/InstSimplify/vec-cmp.ll
    M utils/bazel/llvm-project-overlay/clang/BUILD.bazel

  Log Message:
  -----------
  Rebase

Created using spr 1.3.6-beta.1


Compare: https://github.com/llvm/llvm-project/compare/f5b5db8f0875...c9d96c0d77b6

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