[all-commits] [llvm/llvm-project] 264027: [AArch64] Optimized generated assembly for bool to...

[Lukacma via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 26402777ebf4eb3d8f3d5a45943b451c740b2d76
      https://github.com/llvm/llvm-project/commit/26402777ebf4eb3d8f3d5a45943b451c740b2d76
  Author: Lukacma <Marian.Lukac at arm.com>
  Date:   2024-02-28 (Wed, 28 Feb 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll

  Log Message:
  -----------
  [AArch64] Optimized generated assembly for bool to svbool_t conversions (#83001)

In certain cases Legalizer was generating `AND(WHILELO, SPLAT 1)` instruction pattern, when `WHILELO` would be sufficient.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications