[all-commits] [llvm/llvm-project] 634b02: [llvm][arm] add T1 and T2 assembly options for vll...

[SivanShani-Arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 634b0243b8f7acc85af4f16b70e91d86ded4dc83
      https://github.com/llvm/llvm-project/commit/634b0243b8f7acc85af4f16b70e91d86ded4dc83
  Author: SivanShani-Arm <sivan.shani at arm.com>
  Date:   2024-02-28 (Wed, 28 Feb 2024)

  Changed paths:
    M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    M llvm/lib/Target/ARM/ARMInstrFormats.td
    M llvm/lib/Target/ARM/ARMInstrVFP.td
    M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    M llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
    M llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir
    M llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir
    M llvm/test/MC/ARM/thumbv8m.s
    A llvm/test/MC/ARM/vlstm-vlldm-8.1m.s
    A llvm/test/MC/ARM/vlstm-vlldm-8m.s
    A llvm/test/MC/ARM/vlstm-vlldm-diag.s
    A llvm/test/MC/Disassembler/ARM/armv8.1m-vlldm_vlstm-8.1.main.txt
    A llvm/test/MC/Disassembler/ARM/armv8.1m-vlldm_vlstm-8.main.txt
    M llvm/unittests/Target/ARM/MachineInstrTest.cpp

  Log Message:
  -----------
  [llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (#83116)

T1 allows for an optional registers list, the register list must be {d0-d15}.
T2 defines a mandatory register list, the register list must be {d0-d31}.

The requirements for T1/T2 are as follows:
                T1              T2
Require:        v8-M.Main,      v8.1-M.Main,
                secure state    secure state
16 D Regs       valid           valid
32 D Regs       UNDEFINED       valid
No D Regs       NOP             NOP



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