[all-commits] [llvm/llvm-project] 56183c: [RISCV] Disable lax vector conversions between RVV...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 56183cf608f308ff441b69dcc3ef626acbb014d4
      https://github.com/llvm/llvm-project/commit/56183cf608f308ff441b69dcc3ef626acbb014d4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-26 (Thu, 26 Oct 2023)

  Changed paths:
    M clang/lib/AST/ASTContext.cpp
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-cast.c
    M clang/test/Sema/riscv-rvv-lax-vector-conversions.c
    M clang/test/SemaCXX/riscv-rvv-lax-vector-conversions.cpp

  Log Message:
  -----------
  [RISCV] Disable lax vector conversions between RVVBuiltin types and RVVFixedLengthDataVector.

This seems to be causing issues with using overloaded RVV intrinsics
that take scalar operands. If the scalar type passed in doesn't exactly
match the element type.

I blindly copied this feature from SVE. Since no one has asked for it
I'd prefer to remove it to make overloaded intrinsics work as expected.

By removing the lax conversions, types declared with __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)))
can only ever be used like their underlying RVV builtin type. No lax conversions
to other element sizes with the same LMUL.

Fixes #64404.