[all-commits] [llvm/llvm-project] 696eb3: Remove unnecessary newline from error message

Thu Oct 26 12:12:31 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 696eb3a55aecb6d6a702da9d7d88fbae7b3d77d0
      https://github.com/llvm/llvm-project/commit/696eb3a55aecb6d6a702da9d7d88fbae7b3d77d0
  Author: Alex Richardson <alexrichardson at google.com>
  Date:   2023-10-26 (Thu, 26 Oct 2023)

  Changed paths:
    M llvm/lib/MC/TargetRegistry.cpp

  Log Message:
  -----------
  Remove unnecessary newline from error message

I was writing a test that included this error and noticed the spurios
newline that made writing the test more awkward.

  Commit: e39f6c1844fab59c638d8059a6cf139adb42279a
      https://github.com/llvm/llvm-project/commit/e39f6c1844fab59c638d8059a6cf139adb42279a
  Author: Alex Richardson <alexrichardson at google.com>
  Date:   2023-10-26 (Thu, 26 Oct 2023)

  Changed paths:
    M llvm/test/Analysis/BasicAA/libfuncs.ll
    M llvm/test/Analysis/CostModel/AArch64/sve-fptrunc.ll
    M llvm/test/Analysis/CostModel/AArch64/sve-trunc.ll
    M llvm/test/Analysis/CostModel/AMDGPU/cast.ll
    M llvm/test/Analysis/CostModel/AMDGPU/load-to-trunc.ll
    M llvm/test/Analysis/CostModel/ARM/load-to-trunc.ll
    M llvm/test/Analysis/CostModel/PowerPC/load-to-trunc.ll
    M llvm/test/Analysis/CostModel/RISCV/cast.ll
    M llvm/test/Analysis/CostModel/RISCV/fca-load-store.ll
    M llvm/test/Analysis/CostModel/RISCV/load-to-trunc.ll
    M llvm/test/Analysis/CostModel/RISCV/rvv-load-store.ll
    M llvm/test/Analysis/CostModel/SystemZ/load-to-trunc.ll
    M llvm/test/Analysis/CostModel/X86/load-to-trunc.ll
    M llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll
    M llvm/test/Analysis/CostModel/X86/size-cost.ll
    M llvm/test/Analysis/CostModel/X86/trunc-codesize.ll
    M llvm/test/Analysis/CostModel/X86/trunc-latency.ll
    M llvm/test/Analysis/CostModel/X86/trunc-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/trunc.ll
    M llvm/test/CodeGen/AArch64/arm64_32-gep-sink.ll
    M llvm/test/CodeGen/AArch64/sme-aarch64-svcount-O3.ll
    M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.defined.nobuiltin.ll
    M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
    M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
    M llvm/test/CodeGen/AMDGPU/lds-reject-absolute-addresses.ll
    M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
    M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
    M llvm/test/CodeGen/AMDGPU/lower-kernel-and-module-lds.ll
    M llvm/test/CodeGen/AMDGPU/lower-kernel-lds-super-align.ll
    M llvm/test/CodeGen/AMDGPU/lower-kernel-lds.ll
    M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
    M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll
    M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-indirect-extern-uses-max-reachable-alignment.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-used-list.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
    M llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll
    M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
    M llvm/test/CodeGen/AMDGPU/opencl-printf.ll
    M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
    M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
    M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll
    M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1-bpfeb.ll
    M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1.ll
    M llvm/test/CodeGen/X86/expand-large-div-rem-sdiv129.ll
    M llvm/test/CodeGen/X86/expand-large-div-rem-srem129.ll
    M llvm/test/CodeGen/X86/expand-large-div-rem-udiv129.ll
    M llvm/test/CodeGen/X86/expand-large-div-rem-urem129.ll
    M llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll
    M llvm/test/Instrumentation/SanitizerCoverage/cmp-tracing-api-x86_32.ll
    M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
    M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
    M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmax.ll
    M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmin.ll
    M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fsub.ll
    M llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll
    M llvm/test/Transforms/AtomicExpand/X86/expand-atomic-libcall.ll
    M llvm/test/Transforms/CodeGenPrepare/AMDGPU/sink-addrspacecast.ll
    M llvm/test/Transforms/DivRemPairs/X86/div-expanded-rem-pair.ll
    M llvm/test/Transforms/IndVarSimplify/ARM/indvar-cost.ll
    M llvm/test/Transforms/InferFunctionAttrs/annotate.ll
    M llvm/test/Transforms/InstCombine/double-float-shrink-2.ll
    M llvm/test/Transforms/InstCombine/ffs-i16.ll
    M llvm/test/Transforms/InstCombine/fls-i16.ll
    M llvm/test/Transforms/InstCombine/isascii-i16.ll
    M llvm/test/Transforms/InstCombine/isdigit-i16.ll
    M llvm/test/Transforms/InstCombine/pow-4.ll
    M llvm/test/Transforms/InstCombine/pow_fp_int.ll
    M llvm/test/Transforms/InstCombine/printf-i16.ll
    M llvm/test/Transforms/InstCombine/puts-i16.ll
    M llvm/test/Transforms/InstCombine/sincospi.ll
    M llvm/test/Transforms/InstSimplify/ConstProp/calls-math-finite.ll
    M llvm/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
    M llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll
    M llvm/test/Transforms/LoopUnroll/ARM/instr-size-costs.ll
    M llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-runtime-check-size-based-threshold.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/synthesize-mask-for-call.ll
    M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses-zve32x.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
    M llvm/test/Transforms/MemCpyOpt/no-libcalls.ll
    M llvm/test/Transforms/MergeICmps/X86/addressspaces.ll
    M llvm/test/Transforms/NewGVN/refine-stores.ll
    M llvm/test/Transforms/OpenMP/barrier_removal.ll
    M llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
    M llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
    M llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-add-i64.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/splat-loads.ll
    M llvm/test/Transforms/SLPVectorizer/X86/control-dependence.ll
    M llvm/test/Transforms/SLPVectorizer/X86/opaque-ptr.ll
    M llvm/test/Transforms/SafeStack/X86/setjmp2.ll
    M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn.ll
    M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep.ll
    M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
    M llvm/test/Transforms/SeparateConstOffsetFromGEP/RISCV/split-gep.ll
    M llvm/test/Transforms/TypePromotion/ARM/pointers.ll
    M llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant-inseltpoison.ll
    M llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll
    M llvm/test/Transforms/VectorCombine/X86/scalarize-cmp-inseltpoison.ll
    M llvm/test/Transforms/VectorCombine/X86/scalarize-cmp.ll
    A llvm/test/tools/opt/infer-data-layout.ll
    A llvm/test/tools/opt/invalid-target.ll
    M llvm/tools/opt/opt.cpp

  Log Message:
  -----------
  [opt] Infer DataLayout from triple if not specified

There are many tests that specify a target triple/CPU flags but no
DataLayout which can lead to IR being generated that has unusual
behaviour. This commit attempts to use the default DataLayout based
on the relevant flags if there is no explicit override on the command
line or in the IR file.

One thing that is not currently possible to differentiate from a missing
datalayout `target datalayout = ""` in the IR file since the current
APIs don't allow detecting this case. If it is considered useful to
support this case (instead of passing "-data-layout=" on the command
line), I can change IR parsers to track whether they have seen such a
directive and change the callback type.

Differential Revision: https://reviews.llvm.org/D141060

Compare: https://github.com/llvm/llvm-project/compare/c02b2ab8ab79...e39f6c1844fa