[all-commits] [llvm/llvm-project] bba83e: [AArch64] LowerMUL - use SDValue directly instead ...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bba83e20deec28572dbec4288cd0a135b4386c25
      https://github.com/llvm/llvm-project/commit/bba83e20deec28572dbec4288cd0a135b4386c25
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-09-22 (Fri, 22 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  Log Message:
  -----------
  [AArch64] LowerMUL - use SDValue directly instead of SDNode. NFC.

As discussed on D159537, using the SDValue operands directly instead of peeking inside to the SDNode prevents any issues where a non-zero result index has been used.


  Commit: 6d2679992e58bdb2ab74f354b0b8c9ce2a31f247
      https://github.com/llvm/llvm-project/commit/6d2679992e58bdb2ab74f354b0b8c9ce2a31f247
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-09-22 (Fri, 22 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  Log Message:
  -----------
  [AArch64] Don't rely on (zext (trunc x)) pattern to detect zext_inreg MULL patterns - use value tracking directly

As explained on D159533, I'm trying to generalize the "(zext (trunc x)) -> x iff the upper bits are known zero" fold in getNode() and I was seeing assertions in the aarch64 mull matching code as it was assuming these 'zero-extend-inreg' patterns will remain from earlier in LowerMUL.

Instead I've updated selectUmullSmull/skipExtensionForVectorMULL to just use value tracking to detect when the upper bits are known zero, and to insert the truncation nodes later if necessary.

Differential Revision: https://reviews.llvm.org/D159537


Compare: https://github.com/llvm/llvm-project/compare/23ea98f155b0...6d2679992e58