[all-commits] [llvm/llvm-project] 93fde2: [RISCV] Add a pass to rewrite rd to x0 for non-com...

[Yingwei Zheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 93fde2ea1b2cb07ed5741057571ee38e7e224978
      https://github.com/llvm/llvm-project/commit/93fde2ea1b2cb07ed5741057571ee38e7e224978
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2023-09-20 (Wed, 20 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/CMakeLists.txt
    M llvm/lib/Target/RISCV/RISCV.h
    A llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
    M llvm/test/CodeGen/RISCV/branch.ll
    M llvm/test/CodeGen/RISCV/double-mem.ll
    M llvm/test/CodeGen/RISCV/float-mem.ll
    M llvm/test/CodeGen/RISCV/half-mem.ll
    M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
    M llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
    M llvm/test/CodeGen/RISCV/mem.ll
    M llvm/test/CodeGen/RISCV/mem64.ll
    M llvm/test/CodeGen/RISCV/rvv/localvar.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

  Log Message:
  -----------
  [RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused

When AMOs are used to implement parallel reduction operations, typically the return value would be discarded.
This patch adds a peephole pass `RISCVDeadRegisterDefinitions`. It rewrites `rd` to `x0` when `rd` is marked as dead.
It may improve the register allocation and reduce pipeline hazards on CPUs without register renaming and OOO.
Comparison with GCC: https://godbolt.org/z/bKaxnEcec

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158759