[all-commits] [llvm/llvm-project] 188d5c: [RISCV] Add a combine to form masked.store from un...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 188d5c74426500809a36febe615523e111e9c74e
      https://github.com/llvm/llvm-project/commit/188d5c74426500809a36febe615523e111e9c74e
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-09-19 (Tue, 19 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-load-store-intrinsics.ll

  Log Message:
  -----------
  [RISCV] Add a combine to form masked.store from unit strided store

Add a DAG combine to form a masked.store from a masked_strided_store intrinsic
with stride equal to element size. This is the store analogy to PR #65674.

As seen in the tests, this does pickup a few cases that we'd previously missed
due to selection ordering.  We match strided stores early without going through
the recently added generic mscatter combines, and thus weren't recognizing the
unit strided store.