[all-commits] [llvm/llvm-project] 8f8f44: [RISCV] Recognize veyron-v1 processor in clang dri...

[mgudim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8f8f4493d5fc6a025fff678f030da73dcfd8baa7
      https://github.com/llvm/llvm-project/commit/8f8f4493d5fc6a025fff678f030da73dcfd8baa7
  Author: mgudim <mgudim at gmail.com>
  Date:   2023-09-19 (Tue, 19 Sep 2023)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Recognize veyron-v1 processor in clang driver. (#66703)

Subsequent PRs will add the scheduling model and support for macro
fusions.