[all-commits] [llvm/llvm-project] 2861ec: [AArch64][GlobalISel] Add lowering for constant BI...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2861ec84fce21c2ec9f33849e38661b9f4fe62e2
      https://github.com/llvm/llvm-project/commit/2861ec84fce21c2ec9f33849e38661b9f4fe62e2
  Author: David Green <david.green at arm.com>
  Date:   2023-09-17 (Sun, 17 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Combine.td
    M llvm/lib/Target/AArch64/AArch64InstrGISel.td
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-bit.mir
    M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Add lowering for constant BIT/BIF/BSP (#65897)

The non-constant bit/bif/bsp already work through tablegen patterns, this
patch handles the constant case, mirroring the basic support for
`or(and(X, C), and(Y, ~C))` from ISel tryCombineToBSL. BSP gets expanded
to either BIT, BIF or BSL depending on the best register allocation.
G_BIT can be replaced with G_BSP as a more general alternative.