[all-commits] [llvm/llvm-project] e042ff: [SDAG][RISCV] Avoid expanding is-power-of-2 patter...

[Yingwei Zheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e042ff7eefff6037ffe8350db7c52080a189cce8
      https://github.com/llvm/llvm-project/commit/e042ff7eefff6037ffe8350db7c52080a189cce8
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2023-09-17 (Sun, 17 Sep 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll

  Log Message:
  -----------
  [SDAG][RISCV] Avoid expanding is-power-of-2 pattern on riscv32/64 with zbb

This patch adjusts the legality check for riscv to use `cpop/cpopw` since `isOperationLegal(ISD::CTPOP, MVT::i32)` returns false on rv64gc_zbb.
Clang vs gcc: https://godbolt.org/z/rc3s4hjPh

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D156390