[all-commits] [llvm/llvm-project] 00e794: [clang-format] Properly indent lines inside Verilo...

[sstwcw via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 00e794b4dd9699403f2df3ac9c8147fc139730b2
      https://github.com/llvm/llvm-project/commit/00e794b4dd9699403f2df3ac9c8147fc139730b2
  Author: sstwcw <su3e8a96kzlver at posteo.net>
  Date:   2023-09-16 (Sat, 16 Sep 2023)

  Changed paths:
    M clang/lib/Format/ContinuationIndenter.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp

  Log Message:
  -----------
  [clang-format] Properly indent lines inside Verilog case structure (#65861)

When a statement following a case label had to be broken into multiple
lines, the continuation parts were not indented correctly.

Old:

```Verilog
case (data)
  16'd0:
    result = // break here
    10'b0111111111;
endcase
```

New:

```Verilog
case (data)
  16'd0:
    result = // break here
        10'b0111111111;
endcase
```

Verilog case labels and the following statements are on the same
unwrapped line due to the difficulty of identifying them. So there was a
rule in `getNewLineColumn` to add a level of indentation to the part
following the case label. However, in case the line had to be broken
again, the code at the end of the function would see that the line was
already broken with the continuation part indented, so it would not
indent it more. Now `State.FirstIndent` is changed as well for the part
following the case label, so the logic for determining when to add a
continuation indentation works.