[all-commits] [llvm/llvm-project] b423e1: [SDAG][RISCV] Avoid neg instructions when lowering...

[Yingwei Zheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b423e1f05dc3dc7ca05d1d788d0e6b5d8423b5b6
      https://github.com/llvm/llvm-project/commit/b423e1f05dc3dc7ca05d1d788d0e6b5d8423b5b6
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2023-09-16 (Sat, 16 Sep 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
    M llvm/test/CodeGen/Mips/atomicops.ll
    A llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll

  Log Message:
  -----------
  [SDAG][RISCV] Avoid neg instructions when lowering atomic_load_sub with a constant rhs

This patch avoids creating (sub x0, rhs) when lowering atomic_load_sub with a constant rhs.
Comparison with GCC: https://godbolt.org/z/c5zPdP7j4

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158673