[all-commits] [llvm/llvm-project] 747249: [AArch64] Split Ampere1Write_Arith into rr/ri and ...

David Green via All-commits all-commits at lists.llvm.org
Thu Sep 14 08:29:43 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 74724902ba2fc0dc2734cdb5fae15cb338f1b635
  Author: David Green <david.green at arm.com>
  Date:   2023-09-14 (Thu, 14 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
    A llvm/test/CodeGen/AArch64/ampere1-sched-add.mir

  Log Message:
  [AArch64] Split Ampere1Write_Arith into rr/ri and rs/rx InstRWs. (#66384)

The ampere1 scheduling model uses IsCheapLSL predicates for ADDXri and
ADDWrr instructions, which only have 3 operands. In attempting to check
that the third is a shift, the predicate can attempt to access an out of
bounds operand, hitting an assert. This splits the rr/ri instructions
(which can never have shifts) from the rs/rx instructions to ensure they
both work correctly. Ampere1Write_1cyc_1AB was chosen for the rr/ir
instructions to match the cheap case.

This also sets CompleteModel = 0 for the ampere1 scheduling model, as at
runtime under debug it will attempt to check that as well as all
instructions having scheduling info, there is information for each
output operand.

DefIdx 1 exceeds machine model writes for
  renamable $w9, renamable $w8 = LDPWi renamable $x8, 0
(Try with MCSchedModel.CompleteModel set to false)incomplete machine

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