[all-commits] [llvm/llvm-project] 9ef15f: [AArch64][CodeGen] Fix wrong operand order when cr...
daisy202309 via All-commits
all-commits at lists.llvm.org
Wed Sep 13 21:10:29 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 9ef15f4109890b2ad1e7ac714e4398d44b2087ff
https://github.com/llvm/llvm-project/commit/9ef15f4109890b2ad1e7ac714e4398d44b2087ff
Author: daisy202309 <144047963+daisy202309 at users.noreply.github.com>
Date: 2023-09-14 (Thu, 14 Sep 2023)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-contract.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-fast.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
Log Message:
-----------
[AArch64][CodeGen] Fix wrong operand order when creating vcmla intrinsic (#65278)
Co-authored-by: lizhijin <lizhijin3 at huawei.com>
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