[all-commits] [llvm/llvm-project] 69b056: [PowerPC] Implement SchedModel for Power7

[Qiu Chaofan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 69b056d5638bbe3c8098b5d3a4980eb9929b9bbe
      https://github.com/llvm/llvm-project/commit/69b056d5638bbe3c8098b5d3a4980eb9929b9bbe
  Author: Qiu Chaofan <qiucofan at cn.ibm.com>
  Date:   2023-09-13 (Wed, 13 Sep 2023)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCScheduleP7.td
    M llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
    M llvm/test/CodeGen/PowerPC/aix-lower-jump-table-mir.ll
    M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-char.ll
    M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-double.ll
    M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-float.ll
    M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-int.ll
    M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll
    M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-longlong.ll
    M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-short.ll
    M llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-double.ll
    M llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-float.ll
    M llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-int.ll
    M llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-longlong.ll
    M llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll
    M llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll
    M llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll
    M llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc32.ll
    M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
    M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll
    M llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll
    M llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll
    M llvm/test/CodeGen/PowerPC/all-atomics.ll
    M llvm/test/CodeGen/PowerPC/bswap-load-store.ll
    M llvm/test/CodeGen/PowerPC/builtins-ppc-p8vector.ll
    M llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-move-tofrom-regs.ll
    M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
    M llvm/test/CodeGen/PowerPC/cc.ll
    M llvm/test/CodeGen/PowerPC/crbit-asm.ll
    M llvm/test/CodeGen/PowerPC/crbits.ll
    M llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
    M llvm/test/CodeGen/PowerPC/expand-isel.ll
    M llvm/test/CodeGen/PowerPC/fma-mutate.ll
    M llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
    M llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
    M llvm/test/CodeGen/PowerPC/fsel.ll
    M llvm/test/CodeGen/PowerPC/i1-ext-fold.ll
    M llvm/test/CodeGen/PowerPC/ifcvt.ll
    M llvm/test/CodeGen/PowerPC/load-and-splat.ll
    M llvm/test/CodeGen/PowerPC/machine-combiner.ll
    M llvm/test/CodeGen/PowerPC/peephole-align.ll
    M llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
    M llvm/test/CodeGen/PowerPC/ppc-partword-atomic.ll
    M llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
    M llvm/test/CodeGen/PowerPC/ppc64-calls.ll
    M llvm/test/CodeGen/PowerPC/ppcf128-endian.ll
    M llvm/test/CodeGen/PowerPC/pr61882.ll
    M llvm/test/CodeGen/PowerPC/recipest.ll
    M llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
    M llvm/test/CodeGen/PowerPC/sjlj.ll
    M llvm/test/CodeGen/PowerPC/sms-remark.ll
    M llvm/test/CodeGen/PowerPC/subreg-postra.ll
    M llvm/test/CodeGen/PowerPC/test-vector-insert.ll
    M llvm/test/CodeGen/PowerPC/tls-store2.ll
    M llvm/test/CodeGen/PowerPC/unal-vec-ldst.ll
    M llvm/test/CodeGen/PowerPC/unal4-std.ll
    M llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
    M llvm/test/CodeGen/PowerPC/vavg.ll
    M llvm/test/CodeGen/PowerPC/vec-icmpeq-v2i64-p7.ll
    M llvm/test/CodeGen/PowerPC/vec-min-max.ll
    M llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll
    M llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
    M llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
    M llvm/test/CodeGen/PowerPC/vsx.ll
    M llvm/test/CodeGen/PowerPC/widen-vec-correctly-be.ll

  Log Message:
  -----------
  [PowerPC] Implement SchedModel for Power7

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D158704