[all-commits] [llvm/llvm-project] dc8d2e: [AArch64][SME]Update intrinsic interface for read/...

[CarolineConcatto via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dc8d2ecc5e56318ee2aa9fdb4945a07b26d635a0
      https://github.com/llvm/llvm-project/commit/dc8d2ecc5e56318ee2aa9fdb4945a07b26d635a0
  Author: CarolineConcatto <51754594+CarolineConcatto at users.noreply.github.com>
  Date:   2023-09-12 (Tue, 12 Sep 2023)

  Changed paths:
    M clang/include/clang/Basic/arm_sme.td
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c
    M clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

  Log Message:
  -----------
  [AArch64][SME]Update intrinsic interface for read/write (#65594)

The new ACLE PR#225[1] now combines the slice parameters for some
builtins. This patch is the #2 of 3 patches to update the interface.

Slice specifies the ZA slice number directly and needs to be explicity
implemented by the "user" with the base register plus the immediate
offset

[1]https://github.com/ARM-software/acle/pull/225/files