[all-commits] [llvm/llvm-project] 4793c2: [DAGCombiner][RISCV] Prefer to sext i32 non-negati...

[Yingwei Zheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4793c2c3de79236f5cdfed2a4f3c07026f519571
      https://github.com/llvm/llvm-project/commit/4793c2c3de79236f5cdfed2a4f3c07026f519571
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2023-09-12 (Tue, 12 Sep 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/RISCV/aext-to-sext.ll

  Log Message:
  -----------
  [DAGCombiner][RISCV] Prefer to sext i32 non-negative values (#65984)

By default, `DAGCombiner` folds `sext x` to `zext x` when `x` is
non-negative. It will generate redundant `zext` inst seq on riscv64
(typically `slli (srli x, 32), 32`).
godbolt: https://godbolt.org/z/osf6adP1o
This patch applies the transform iff `zext` is **cheaper** than `sext`.