[all-commits] [llvm/llvm-project] 806761: [test] Change llc -march= to -mtriple=

Fangrui Song via All-commits all-commits at lists.llvm.org
Mon Sep 11 14:42:52 PDT 2023 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 806761a7629df268c8aed49657aeccffa6bca449
      https://github.com/llvm/llvm-project/commit/806761a7629df268c8aed49657aeccffa6bca449
  Author: Fangrui Song <i at maskray.me>
  Date:   2023-09-11 (Mon, 11 Sep 2023)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd-with-ret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
    M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
    M llvm/test/CodeGen/AMDGPU/build_vector.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
    M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
    M llvm/test/CodeGen/AMDGPU/debug.ll
    M llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
    M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
    M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
    M llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
    M llvm/test/CodeGen/AMDGPU/elf-header-flags-xnack.ll
    M llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll
    M llvm/test/CodeGen/AMDGPU/elf.ll
    M llvm/test/CodeGen/AMDGPU/elf.metadata.ll
    M llvm/test/CodeGen/AMDGPU/elf.r600.ll
    M llvm/test/CodeGen/AMDGPU/extload-align.ll
    M llvm/test/CodeGen/AMDGPU/extload.ll
    M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
    M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
    M llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
    M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
    M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
    M llvm/test/CodeGen/AMDGPU/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/gfx902-without-xnack.ll
    M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
    M llvm/test/CodeGen/AMDGPU/hsa-default-device.ll
    M llvm/test/CodeGen/AMDGPU/imm16.ll
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
    M llvm/test/CodeGen/AMDGPU/kernel-args.ll
    M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
    M llvm/test/CodeGen/AMDGPU/lds-alignment.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
    M llvm/test/CodeGen/AMDGPU/load-global-f64.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-local-f64.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
    M llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
    M llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll
    M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
    M llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
    M llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
    M llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
    M llvm/test/CodeGen/AMDGPU/nullptr.ll
    M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
    M llvm/test/CodeGen/AMDGPU/private-element-size.ll
    M llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll
    M llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
    M llvm/test/CodeGen/AMDGPU/register-count-comments.ll
    M llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
    M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
    M llvm/test/CodeGen/AMDGPU/setcc.ll
    M llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/sra.ll
    M llvm/test/CodeGen/AMDGPU/store-global.ll
    M llvm/test/CodeGen/AMDGPU/store-local.ll
    M llvm/test/CodeGen/AMDGPU/tex-clause-antidep.ll
    M llvm/test/CodeGen/AMDGPU/trap-abis.ll
    M llvm/test/CodeGen/AMDGPU/trap.ll
    M llvm/test/CodeGen/AMDGPU/udiv.ll
    M llvm/test/CodeGen/AMDGPU/unknown-processor.ll
    M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
    M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
    M llvm/test/CodeGen/AMDGPU/vector-alloca.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
    M llvm/test/CodeGen/AVR/ctors.ll
    M llvm/test/CodeGen/AVR/jmp-long.ll
    M llvm/test/CodeGen/AVR/rust-trait-object.ll
    M llvm/test/CodeGen/AVR/sections.ll
    M llvm/test/CodeGen/BPF/BTF/align.ll
    M llvm/test/CodeGen/BPF/BTF/binary-format.ll
    M llvm/test/CodeGen/BPF/elf-symbol-information.ll
    M llvm/test/CodeGen/BPF/objdump_atomics.ll
    M llvm/test/CodeGen/BPF/objdump_cond_op.ll
    M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
    M llvm/test/CodeGen/BPF/objdump_dis_all.ll
    M llvm/test/CodeGen/BPF/objdump_fi_ri.ll
    M llvm/test/CodeGen/BPF/objdump_imm_hex.ll
    M llvm/test/CodeGen/BPF/objdump_intrinsics.ll
    M llvm/test/CodeGen/BPF/objdump_nop.ll
    M llvm/test/CodeGen/BPF/objdump_static_var.ll
    M llvm/test/CodeGen/BPF/objdump_trivial.ll
    M llvm/test/CodeGen/BPF/objdump_two_funcs.ll
    M llvm/test/CodeGen/BPF/reloc-2.ll
    M llvm/test/CodeGen/BPF/reloc-3.ll
    M llvm/test/CodeGen/BPF/reloc-btf-2.ll
    M llvm/test/CodeGen/BPF/reloc-btf.ll
    M llvm/test/CodeGen/BPF/reloc.ll
    M llvm/test/CodeGen/Hexagon/S3_2op.ll
    M llvm/test/CodeGen/Hexagon/cmp.ll
    M llvm/test/CodeGen/Hexagon/compound.ll
    M llvm/test/CodeGen/Hexagon/dualstore.ll
    M llvm/test/CodeGen/Hexagon/duplex.ll
    M llvm/test/CodeGen/Hexagon/extlow.ll
    M llvm/test/CodeGen/Hexagon/relax.ll
    M llvm/test/CodeGen/Hexagon/simple_addend.ll
    M llvm/test/CodeGen/Hexagon/tc_duplex_asm.ll
    M llvm/test/CodeGen/Hexagon/vect-regpairs.ll
    M llvm/test/CodeGen/Hexagon/vrcmpys.ll
    M llvm/test/CodeGen/Mips/2008-07-22-Cstpool.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/shift.ll
    M llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
    M llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
    M llvm/test/CodeGen/Mips/dsp-spill-reload.ll
    M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-l1.ll
    M llvm/test/CodeGen/Mips/mature-mc-support.ll
    M llvm/test/CodeGen/Mips/micromips-atomic1.ll
    M llvm/test/CodeGen/Mips/micromips-b-range.ll
    M llvm/test/CodeGen/Mips/micromips-eva.mir
    M llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
    M llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
    M llvm/test/CodeGen/SPARC/mature-mc-support.ll
    M llvm/test/CodeGen/SPARC/missing-sret.ll
    M llvm/test/CodeGen/XCore/codemodel.ll
    M llvm/test/CodeGen/XCore/epilogue_prologue.ll
    M llvm/test/CodeGen/XCore/scavenging.ll

  Log Message:
  -----------
  [test] Change llc -march= to -mtriple=

The issue is uncovered by #47698: for IR files without a target triple,
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense, e.g. riscv64-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead
of rejecting it outrightly.

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