[all-commits] [llvm/llvm-project] 996171: [mlir][openacc] Model acc cache directive as data ...

[Valentin Clement (バレンタイン クレメン) via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 996171a4122e1ba482010e9c3b9cc3e894a65a84
      https://github.com/llvm/llvm-project/commit/996171a4122e1ba482010e9c3b9cc3e894a65a84
  Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
  Date:   2023-09-11 (Mon, 11 Sep 2023)

  Changed paths:
    M flang/lib/Lower/OpenACC.cpp
    M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
    M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
    M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
    M mlir/test/Dialect/OpenACC/ops.mlir

  Log Message:
  -----------
  [mlir][openacc] Model acc cache directive as data entry operands on acc.loop (#65521)

The `cache` directive may appear at the top of (inside of) a loop. It
specifies array elements or subarrays that should be fetched into the
highest level of the cache for the body of the loop.

The `cache` directive is modeled as a data entry operands attached to
the acc.loop operation.