[all-commits] [llvm/llvm-project] 5352c7: [RISCV] Add a combine to form masked.load from uni...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5352c7939806b19429f6c7918c400be43797b4c7
      https://github.com/llvm/llvm-project/commit/5352c7939806b19429f6c7918c400be43797b4c7
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-09-11 (Mon, 11 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-load-store-intrinsics.ll

  Log Message:
  -----------
  [RISCV] Add a combine to form masked.load from unit strided load (#65674)

Add a DAG combine to form a masked.load from a masked_strided_load
intrinsic with stride equal to element size. This covers a couple of
extra test cases, and allows us to simplify and common some existing
code on the concat_vector(load, ...) to strided load transform.

This is the first in a mini-patch series to try and generalize our
strided load and gather matching to handle more cases, and common up
different approaches to the same problems in different places.