[all-commits] [llvm/llvm-project] 4083ec: [RISCV] Cleanups in CORE-V (xcv) extensions

[Simon Cook via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4083ecfd7f5e13f7906c9d2deafeb6e20ce95b16
      https://github.com/llvm/llvm-project/commit/4083ecfd7f5e13f7906c9d2deafeb6e20ce95b16
  Author: Simon Cook <simon.cook at embecosm.com>
  Date:   2023-07-14 (Fri, 14 Jul 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    M llvm/test/MC/RISCV/corev/XCVbitmanip.s
    M llvm/test/MC/RISCV/corev/XCVmac-valid.s

  Log Message:
  -----------
  [RISCV] Cleanups in CORE-V (xcv) extensions

This is a mostly NFC change cleaning up and clarifying components of the
in-tree CORE-V (xcv*) extensions following discussions on the remaining
extensions.

This makes the following changes to the xcbitmanip and xcvmac support:

1. Add missing extensions from RISCVISAInfo, such that they can be
   supported in clang's -march option.
2. Clarify the extension version number is 1.0.0 in documentation.
3. Clarify the extensions are by OpenHW Group, and the capitilization
   of the CORE-V extension family.
4. Add CORE-V to extension name in RISCVFeatures, both to be consistent
   with other vendors, and also better distinguish e.g. CORE-V bit
   manipulation vs RISC-V's standard Zb extensions.

Differential Revision: https://reviews.llvm.org/D155283