[all-commits] [llvm/llvm-project] 0d3eee: [RISCV] Add support for custom CSRs for Sifive S76.

garvit gupta via All-commits all-commits at lists.llvm.org
Fri Jul 14 09:51:35 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0d3eee33f262402562a1ff28106dbb2f59031bdb
  Author: Garvit Gupta <quic_garvgupt at quicinc.com>
  Date:   2023-07-14 (Fri, 14 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/test/MC/RISCV/machine-csr-names.s
    M llvm/test/MC/RISCV/xsfcie-invalid.s
    M llvm/test/MC/RISCV/xsfcie-valid.s

  Log Message:
  [RISCV] Add support for custom CSRs for Sifive S76.

Support for below CSRs is addeed -
1. Branch Prediction Mode CSR
2. Feature Disable CSR
3. Power Dial CSR


This patch removes AltName field from SysReg class because we are now using
separate class for custom vendor CSRs. Also, all use of AltName have been changed
to DeprecatedName because both were interchangeably used for old names which are
not in use in latest RISCV spec.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153499

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