[all-commits] [llvm/llvm-project] 2ac992: [RISCV] Narrow types of index operand matched patt...
Yeting Kuo via All-commits
all-commits at lists.llvm.org
Fri Jul 14 00:46:00 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 2ac99205ee1a232b8da5ec144662b29bb00ccd70
https://github.com/llvm/llvm-project/commit/2ac99205ee1a232b8da5ec144662b29bb00ccd70
Author: Yeting Kuo <yeting.kuo at sifive.com>
Date: 2023-07-14 (Fri, 14 Jul 2023)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
A llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
Log Message:
-----------
[RISCV] Narrow types of index operand matched pattern (shl (zext), C).
(shl (zext to iXLenVec), C) is a possible pattern in auto-vectorized code for
indexed loads/stores. But extending to iXLen might be too aggressive, RVV
indexed load/store instructions zero extend their indexed operand to XLEN.
The patch tries to narrow the type of the zero extension. It's benefit to
decrease register pressure.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D154687
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