[all-commits] [llvm/llvm-project] 55e277: [RISCV] Add initial SDNode patterns for unary zvbb...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 55e2772e9f518af7762ddb62da6bcaacecc1462b
      https://github.com/llvm/llvm-project/commit/55e2772e9f518af7762ddb62da6bcaacecc1462b
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-13 (Thu, 13 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll

  Log Message:
  -----------
  [RISCV] Add initial SDNode patterns for unary zvbb instructions

This patch adds pseudos and SDNode patterns for vbrev.v, vrev8.v, vclz.v,
vctz.v and vcpop.v.
I've only added them for integer element types so far since we're lacking tests
for floats.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155216