[all-commits] [llvm/llvm-project] 201cf5: [RISCV] Correct resource cycles for vzext/vsext in...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 201cf545ad71f1450f0d26ef3bde5ea25afc28de
      https://github.com/llvm/llvm-project/commit/201cf545ad71f1450f0d26ef3bde5ea25afc28de
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-13 (Thu, 13 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

  Log Message:
  -----------
  [RISCV] Correct resource cycles for vzext/vsext in SiFive7 scheduler.

The instructions produce DLEN bits per cycle. The vsetvli LMUL for these
instructions is the output EMUL. The input EMUL is scaled down by
the vector factor suffix on the instruction name.

So for LMUL=1 there are 2*DLEN bits of result produced over 2 cycles.
This makes SiFive7GetCyclesDefault the correct resource cycles.

Reviewed By: monkchiang

Differential Revision: https://reviews.llvm.org/D155010