[all-commits] [llvm/llvm-project] 50378a: [AArch64] Extra tablegen patterns for smaller extr...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 50378a16d41209545022975fb253a0ce2d9597cc
      https://github.com/llvm/llvm-project/commit/50378a16d41209545022975fb253a0ce2d9597cc
  Author: David Green <david.green at arm.com>
  Date:   2023-07-13 (Thu, 13 Jul 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
    M llvm/test/CodeGen/AArch64/arm64-ld1.ll
    M llvm/test/CodeGen/AArch64/extbinopload.ll
    M llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
    M llvm/test/CodeGen/AArch64/neon-extadd.ll
    M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll

  Log Message:
  -----------
  [AArch64] Extra tablegen patterns for smaller extracted addl/addw/subl/subw

During lowering, especially of smaller vector types, we can end up with
`add (extract_subvector(zext(x), extract_subvector(zext(y))`, which can
be turned into `extract_subvector(add(zext(y), zext(x)))`, which can use
the addl AArch64 instruction. This adds some tablegen patterns for it,
along with addw where only one operand is an extract/extend and subl/subw.

Differential Revision: https://reviews.llvm.org/D153632