[all-commits] [llvm/llvm-project] 2c38d6: [8/8][RISCV] Add rounding mode control variant for...

[Yueh-Ting (eop) Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2c38d6332345eddb7ed0509052383dc12faef767
      https://github.com/llvm/llvm-project/commit/2c38d6332345eddb7ed0509052383dc12faef767
  Author: eopXD <yueh.ting.chen at gmail.com>
  Date:   2023-07-13 (Thu, 13 Jul 2023)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/lib/Sema/SemaChecking.cpp
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfredosum-out-of-range.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfredusum-out-of-range.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwredosum-out-of-range.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwredusum-out-of-range.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll

  Log Message:
  -----------
  [8/8][RISCV] Add rounding mode control variant for vfredosum, vfredusum, vfwredosum, vfwredusum

Depends on D154635

For the cover letter of the patch-set, please checkout D154628.

This is the 8th patch of the patch-set.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154636