[all-commits] [llvm/llvm-project] 5d18d4: [7/8][RISCV] Add rounding mode control variant for...

[Yueh-Ting (eop) Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5d18d43f26ad8c0636c20008cd0ca855940c4a3d
      https://github.com/llvm/llvm-project/commit/5d18d43f26ad8c0636c20008cd0ca855940c4a3d
  Author: eopXD <yueh.ting.chen at gmail.com>
  Date:   2023-07-13 (Thu, 13 Jul 2023)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/lib/Sema/SemaChecking.cpp
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfcvt-out-of-range.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfncvt-out-of-range.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwcvt-out-of-range.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll

  Log Message:
  -----------
  [7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer

Depends on D154634

For the cover letter of the patch-set, please checkout D154628.

This is the 7th patch of the patch-set. This patch includes change to
vfcvt_x_f, vfcvt_xu_f, vfwcvt_x_f, vfwcvt_xu_f, vfncvt_x_f, vfncvt_xu_f
vfcvt_f_x, vfcvt_f_xu, vfncvt_f_x vfncvt_f_xu, vfncvt_f_f

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154635