[all-commits] [llvm/llvm-project] 1a905e: [3/8][RISCV] Add rounding mode control variant for...

[Yueh-Ting (eop) Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1a905e82389264fd8ed9a1dee052e46cb03c9709
      https://github.com/llvm/llvm-project/commit/1a905e82389264fd8ed9a1dee052e46cb03c9709
  Author: eopXD <yueh.ting.chen at gmail.com>
  Date:   2023-07-13 (Thu, 13 Jul 2023)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/lib/Sema/SemaChecking.cpp
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfdiv-out-of-range.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfmul-out-of-range.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfrdiv-out-of-range.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwmul-out-of-range.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
    M llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

  Log Message:
  -----------
  [3/8][RISCV] Add rounding mode control variant for vfmul, vfdiv, vfrdiv, vfwmul

Depends on D154629

For the cover letter of the patch-set, please checkout D154628.

This is the 3rd patch of the patch-set.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154631