[all-commits] [llvm/llvm-project] b97562: [RISCV] Test case for D147268. NFC

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b9756260eea1c225e4c829127e55aeb974322ae8
      https://github.com/llvm/llvm-project/commit/b9756260eea1c225e4c829127e55aeb974322ae8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-03-30 (Thu, 30 Mar 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll

  Log Message:
  -----------
  [RISCV] Test case for D147268. NFC

This test currently miscompiles.


  Commit: f2315545b2e4232afab636adb384a4a8e971b94e
      https://github.com/llvm/llvm-project/commit/f2315545b2e4232afab636adb384a4a8e971b94e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-03-30 (Thu, 30 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll

  Log Message:
  -----------
  [RISCV] Correct the EvenSrc/OddSrc computation in isInterleaveShuffle.

StartIndexes[0] Tells exactly which source element is in element 0,
the even source. Nothing needs to be swapped.

Since we're dealing with power of 2 vector lengths, StartIndexes[0]
is almost always even so the condition here was never true. The
exception is when we're interleaving two 1 element vectors. In that
case StartIndexes[0] could be 1.

We recently hit a failure from this on a pulldown. I don't have
the reduced reproducer yet and my naive attempts at making an
interleave of 1 element vectors produces a slideup instead so don't
go through this path.

Reviewed By: luke

Differential Revision: https://reviews.llvm.org/D147268


Compare: https://github.com/llvm/llvm-project/compare/dc90af501f00...f2315545b2e4