[all-commits] [llvm/llvm-project] dc90af: [RISCV] Bump I, F, D, and A extension versions to ...
Craig Topper via All-commits
all-commits at lists.llvm.org
Thu Mar 30 15:29:04 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: dc90af501f00bb0bbbfde2d90360f074922e3e81
https://github.com/llvm/llvm-project/commit/dc90af501f00bb0bbbfde2d90360f074922e3e81
Author: Craig Topper <craig.topper at sifive.com>
Date: 2023-03-30 (Thu, 30 Mar 2023)
Changed paths:
M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
M clang/test/Driver/riscv-arch.c
M clang/test/Preprocessor/riscv-target-features.c
M lld/test/ELF/lto/riscv-attributes.ll
M lld/test/ELF/riscv-attributes.s
M llvm/docs/ReleaseNotes.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/attribute-with-insts.s
M llvm/test/MC/RISCV/attribute-with-option.s
M llvm/test/MC/RISCV/attribute.s
M llvm/test/MC/RISCV/invalid-attribute.s
M llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Bump I, F, D, and A extension versions to 20191214 spec version
New versions I2.1, F2.2, D2.2 A2.1
Make F and Zfinx imply Zicsr.
Make G imply Zifencei.
This should have no impact to generated code. We have no plans to require Zicsr/Zifencei extension to be explicitly enabled to use Zicsr/Zifencei instructions in assembly.
See https://reviews.llvm.org/D147183 for documentation regarding what version specification we implement.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D147179
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