[all-commits] [llvm/llvm-project] 96a7e0: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVPro...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 96a7e057567d3aaaa7e7c65cfce00430ad383a1b
      https://github.com/llvm/llvm-project/commit/96a7e057567d3aaaa7e7c65cfce00430ad383a1b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-03-30 (Thu, 30 Mar 2023)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

I only added Zicsr to CPUs that didn't already have an implication
through the F extension.

As far as I could tell from searching Rocket and Syntacore repositories,
all the CPUs support these instructions.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D147261