[all-commits] [llvm/llvm-project] a66bc1: [DAGCombiner] Avoid converting (x or/xor const) + ...

[Juneyoung Lee via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a66bc1c4a30ca958fee094bd7dcb6bc4b9cdd49f
      https://github.com/llvm/llvm-project/commit/a66bc1c4a30ca958fee094bd7dcb6bc4b9cdd49f
  Author: Juneyoung Lee <aqjune at gmail.com>
  Date:   2023-03-08 (Wed, 08 Mar 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    A llvm/test/CodeGen/AArch64/add-i256.ll

  Log Message:
  -----------
  [DAGCombiner] Avoid converting (x or/xor const) + y to (x + y) + const if benefit is unclear

This patch resolves suboptimal code generation reported by https://github.com/llvm/llvm-project/issues/60571 .

DAGCombiner currently converts `(x or/xor const) + y` to `(x + y) + const` if this is valid.
However, if `.. + const` is broken down into a sequences of adds with carries, the benefit is not clear, introducing two more add(-with-carry) ops (total 6) in the case of the reported issue whereas the optimal sequence must only have 4 add(-with-carry)s.

This patch resolves this issue by allowing this conversion only when (1) `.. + const` is legal or promotable, or (2) `const` is a sign bit because it does not introduce more adds.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D144116