[all-commits] [llvm/llvm-project] aca34d: Prioritize lowering V{4|16}F32 with blend.

Fri Feb 24 13:22:33 PST 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aca34da46da41792614799a8b6a8b31a5a6e23d9
      https://github.com/llvm/llvm-project/commit/aca34da46da41792614799a8b6a8b31a5a6e23d9
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-24 (Fri, 24 Feb 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/avx512-insert-extract.ll
    M llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll

  Log Message:
  -----------
  Prioritize lowering V{4|16}F32 with blend.

Blend is often fastest available instruction so it should be higher
priority for v4f32 and an option for v16f32.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D143856

  Commit: 5767497943c719e7b9fd319d73f9a33b4e0f8595
      https://github.com/llvm/llvm-project/commit/5767497943c719e7b9fd319d73f9a33b4e0f8595
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-24 (Fri, 24 Feb 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/pr43866.ll
    M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
    M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll

  Log Message:
  -----------
  Add Extend shuffle pattern to vNf32 shuffles.

There are some cases where its useful for float types, not quite as
hot as in the integer case, but still better than alternatives.

Differential Revision: https://reviews.llvm.org/D143785

  Commit: 015b3817ca1ee56015bc7b510c1bfa68700e63b7
      https://github.com/llvm/llvm-project/commit/015b3817ca1ee56015bc7b510c1bfa68700e63b7
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-24 (Fri, 24 Feb 2023)

  Changed paths:
    A llvm/test/CodeGen/X86/shuffle-as-shifts.ll

  Log Message:
  -----------
  Add tests for shuffle as shift/rotate; NFC

Differential Revision: https://reviews.llvm.org/D143857

  Commit: 890eb4f0a150bce6e4057e946b8d9c0ba5f811fe
      https://github.com/llvm/llvm-project/commit/890eb4f0a150bce6e4057e946b8d9c0ba5f811fe
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-24 (Fri, 24 Feb 2023)

  Changed paths:
    A llvm/test/Transforms/InstCombine/minmax-of-xor-x.ll

  Log Message:
  -----------
  Add tests for transforming `(max/min (xor X, Pow2), X)`; NFC

Differential Revision: https://reviews.llvm.org/D144605

  Commit: f35e3fa53bb7173a8f8ccda8eb017a7ccd986800
      https://github.com/llvm/llvm-project/commit/f35e3fa53bb7173a8f8ccda8eb017a7ccd986800
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-24 (Fri, 24 Feb 2023)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
    M llvm/test/Transforms/InstCombine/minmax-of-xor-x.ll

  Log Message:
  -----------
  Add transforms for `(max/min (xor X, Pow2), X)` -> `(and/or X, Pow2/~Pow2)`

X ^ Pow2 is guranteed to flip one bit. We can use this to speedup
max/min by just selecting X with/without (or/andnot) the flipped bit
respectively.

Alive2 Links:
smax-neg: https://alive2.llvm.org/ce/z/j3QYFs
smin-neg: https://alive2.llvm.org/ce/z/bFYnQW
smax-pos: https://alive2.llvm.org/ce/z/4xYSxR
smin-pos: https://alive2.llvm.org/ce/z/H3RPKj
umax    : https://alive2.llvm.org/ce/z/P4oRcX
umin    : https://alive2.llvm.org/ce/z/vWZG6p

Differential Revision: https://reviews.llvm.org/D144606

  Commit: 85e83058212b5c78f2a285182feb3ac77f189ba6
      https://github.com/llvm/llvm-project/commit/85e83058212b5c78f2a285182feb3ac77f189ba6
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-24 (Fri, 24 Feb 2023)

  Changed paths:
    A llvm/test/CodeGen/X86/icmp-pow2-diff.ll

  Log Message:
  -----------
  Add tests for (or/and (icmp eq/ne A, C0), (icmp eq/ne A, C1)) where IsPow2(dif(C0, C1)); NFC

Differential Revision: https://reviews.llvm.org/D144282

  Commit: 8c74c5402f6dd400163fed7c3b39a376fa9e9dc1
      https://github.com/llvm/llvm-project/commit/8c74c5402f6dd400163fed7c3b39a376fa9e9dc1
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-24 (Fri, 24 Feb 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/icmp-pow2-diff.ll
    M llvm/test/CodeGen/X86/setcc-logic.ll

  Log Message:
  -----------
  Make `(and/or (icmp eq/ne A,C0), (icmp eq/ne A,C1))` where `IsPow(dif(C0,C1))` work for more patterns.

`(and/or (icmp eq/ne A,C0), (icmp eq/ne A,C1))` can be lowered to
`(icmp eq/ne (and (sub A, (smin C0, C1)), (not (sub (smax C0, C1), (smin C0, C1)))), 0)`
generically if `(sub (smax C0, C1), (smin C0,C1))` is a power of 2.

This covers the existing case of `(and/or (icmp eq/ne A, C_Pow2),(icmp eq/ne A, -C_Pow2))`
as well as other cases.

Alive2 Links:
EQ: https://alive2.llvm.org/ce/z/mLJiUW
NE: https://alive2.llvm.org/ce/z/TKnzUr

Differential Revision: https://reviews.llvm.org/D144283

  Commit: e981e6d10ed323b8cb9ea1f82723bf3009f0bfc3
      https://github.com/llvm/llvm-project/commit/e981e6d10ed323b8cb9ea1f82723bf3009f0bfc3
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-24 (Fri, 24 Feb 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/icmp-pow2-diff.ll

  Log Message:
  -----------
  Add transform for `(and/or (icmp eq/ne A,-1),(icmp eq/ne A,-1+C))`->`(and/or (icmp eq/ne (and ~A,-1+C),0))`

This works of `-1+C` is a negative power of 2.

This can be more useful than the `AddAnd` case as `~A` does not
necessarily require materializing a constant. This makes the transform
worth it for X86 vector types.

Alive2 Links:
EQ: https://alive2.llvm.org/ce/z/P6u8cq
NE: https://alive2.llvm.org/ce/z/_Kkqp1

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D144284

Compare: https://github.com/llvm/llvm-project/compare/f1c8b72c13f1...e981e6d10ed3