[all-commits] [llvm/llvm-project] 16a6cf: [RISCV] Add vendor-defined XTheadSync (Multi-core ...

[Philipp Tomsich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 16a6cf6a99c247375f2f95a922d59da81de81a2c
      https://github.com/llvm/llvm-project/commit/16a6cf6a99c247375f2f95a922d59da81de81a2c
  Author: Manolis Tsamis <manolis.tsamis at vrull.eu>
  Date:   2023-02-22 (Wed, 22 Feb 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    A llvm/test/MC/RISCV/xtheadsync-invalid.s
    A llvm/test/MC/RISCV/xtheadsync-valid.s

  Log Message:
  -----------
  [RISCV] Add vendor-defined XTheadSync (Multi-core synchronization) extension

The vendor-defined XTheadSync (no comparable standard extension exists
at the time of writing) extension adds multi-core synchronization
instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=547c18d9bb95571261dbd17f4767194037eb82bd

Depends on D144496

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144501