[all-commits] [llvm/llvm-project] b02b1e: [LV][NFC] Use ElementCount for getMaxInterleaveFactor

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b02b1e0ed6720a8a019c4468424c830c49b1e981
      https://github.com/llvm/llvm-project/commit/b02b1e0ed6720a8a019c4468424c830c49b1e981
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-02-22 (Wed, 22 Feb 2023)

  Changed paths:
    M llvm/include/llvm/Analysis/TargetTransformInfo.h
    M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
    M llvm/include/llvm/CodeGen/BasicTTIImpl.h
    M llvm/lib/Analysis/TargetTransformInfo.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
    M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
    M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
    M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
    M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
    M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
    M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/lib/Target/X86/X86TargetTransformInfo.h
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

  Log Message:
  -----------
  [LV][NFC] Use ElementCount for getMaxInterleaveFactor

In order to allow targets to disable interleaving for scalable vectors, pass the entire VF's ElementCount to getMaxInterleaveFactor.
This is based off of the approach used here: https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi/-/commit/8d36708507b3c378078b9fe364bc548354aaec86

The plan would then be to disable interleaving on scalable VFs on RISC-V in a follow up patch.
See https://reviews.llvm.org/D143723#4132349

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D144474


  Commit: 15f9cf164c00490484a06032182612474f723fbc
      https://github.com/llvm/llvm-project/commit/15f9cf164c00490484a06032182612474f723fbc
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-02-22 (Wed, 22 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll

  Log Message:
  -----------
  [LV][RISCV] Don't interleave scalable vector loops

It's less clear with scalable vectors than fixed length vectors that
interleaving exposes more ILP, as scalable vectors can be thought of a
sort of hardware form of interleaving, especially with larger LMULs.
This also addresses the unexpected additional unrolling that occurs when
using larger LMULs in the loop vectorizer.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144485


Compare: https://github.com/llvm/llvm-project/compare/28ee6040710f...15f9cf164c00